A Hypercube Design on Wafer-Scale Integration.

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Bibliographic Details
Title:	A Hypercube Design on Wafer-Scale Integration.
Authors:	Ito, Hideo¹, Suzuki, Nobuyuki¹
Source:	Systems & Computers in Japan. 3/1/91, Vol. 22 Issue 4, p29-40. 12p.
Subjects:	Wafer-scale integration of circuits, Systolic array circuits, Hypercube networks (Computer networks), Parallel processing, Computer architecture, Computer systems
Abstract:	This paper proposes a hypercube network (HC) design on the wafer-scale LSI (WSI). HC is considered interesting as a network structure, which is suited to the general or dedicated parallel processing machine. There also exist commercial HC machines. With the development of LSI fabrication technologies as the background, NSI is now feasible where a large-scale parallel processing system is installed on a wafer. The major problems in WSI are how to build in the required network structure on the planar structure wafer, and how to improve the yield by avoiding the defects generated in the fabrication process. In most of the past studies, the array (lattice) structure is employed in the realization of the network on NSI, and HC is seldom employed. In this paper sub-HC with 2p PEs is constructed as the row network (RN); and by connecting 2d-p RNs along the column direction, HC with 2d PEs is constructed. In other words, RN is constructed by the Diogenes method to compose an HC as a one-dimensional structure, and then the structure is extended to two dimensions by adding new switches and bus structures, resulting in a structure suited to WSI. Two structures are considered: the structure with redundant PE only in RN and the structure containing redundant RNs. A rough evaluation for the yield also is presented. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	This paper proposes a hypercube network (HC) design on the wafer-scale LSI (WSI). HC is considered interesting as a network structure, which is suited to the general or dedicated parallel processing machine. There also exist commercial HC machines. With the development of LSI fabrication technologies as the background, NSI is now feasible where a large-scale parallel processing system is installed on a wafer. The major problems in WSI are how to build in the required network structure on the planar structure wafer, and how to improve the yield by avoiding the defects generated in the fabrication process. In most of the past studies, the array (lattice) structure is employed in the realization of the network on NSI, and HC is seldom employed. In this paper sub-HC with 2p PEs is constructed as the row network (RN); and by connecting 2d-p RNs along the column direction, HC with 2d PEs is constructed. In other words, RN is constructed by the Diogenes method to compose an HC as a one-dimensional structure, and then the structure is extended to two dimensions by adding new switches and bus structures, resulting in a structure suited to WSI. Two structures are considered: the structure with redundant PE only in RN and the structure containing redundant RNs. A rough evaluation for the yield also is presented. [ABSTRACT FROM AUTHOR]
ISSN:	08821666
DOI:	10.1002/scj.4690220404