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A Hypercube Design on Wafer-Scale Integration.

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Title: A Hypercube Design on Wafer-Scale Integration.
Authors: Ito, Hideo1, Suzuki, Nobuyuki1
Source: Systems & Computers in Japan. 3/1/91, Vol. 22 Issue 4, p29-40. 12p.
Subjects: Wafer-scale integration of circuits, Systolic array circuits, Hypercube networks (Computer networks), Parallel processing, Computer architecture, Computer systems
Abstract: This paper proposes a hypercube network (HC) design on the wafer-scale LSI (WSI). HC is considered interesting as a network structure, which is suited to the general or dedicated parallel processing machine. There also exist commercial HC machines. With the development of LSI fabrication technologies as the background, NSI is now feasible where a large-scale parallel processing system is installed on a wafer. The major problems in WSI are how to build in the required network structure on the planar structure wafer, and how to improve the yield by avoiding the defects generated in the fabrication process. In most of the past studies, the array (lattice) structure is employed in the realization of the network on NSI, and HC is seldom employed. In this paper sub-HC with 2p PEs is constructed as the row network (RN); and by connecting 2d-p RNs along the column direction, HC with 2d PEs is constructed. In other words, RN is constructed by the Diogenes method to compose an HC as a one-dimensional structure, and then the structure is extended to two dimensions by adding new switches and bus structures, resulting in a structure suited to WSI. Two structures are considered: the structure with redundant PE only in RN and the structure containing redundant RNs. A rough evaluation for the yield also is presented. [ABSTRACT FROM AUTHOR]
Copyright of Systems & Computers in Japan is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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Header DbId: egs
DbLabel: Engineering Source
An: 13988554
AccessLevel: 6
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PubTypeId: academicJournal
PreciseRelevancyScore: 0
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: A Hypercube Design on Wafer-Scale Integration.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Ito%2C+Hideo%22">Ito, Hideo</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Suzuki%2C+Nobuyuki%22">Suzuki, Nobuyuki</searchLink><relatesTo>1</relatesTo>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Systems+%26+Computers+in+Japan%22">Systems & Computers in Japan</searchLink>. 3/1/91, Vol. 22 Issue 4, p29-40. 12p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Wafer-scale+integration+of+circuits%22">Wafer-scale integration of circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Systolic+array+circuits%22">Systolic array circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Hypercube+networks+%28Computer+networks%29%22">Hypercube networks (Computer networks)</searchLink><br /><searchLink fieldCode="DE" term="%22Parallel+processing%22">Parallel processing</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+systems%22">Computer systems</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: This paper proposes a hypercube network (HC) design on the wafer-scale LSI (WSI). HC is considered interesting as a network structure, which is suited to the general or dedicated parallel processing machine. There also exist commercial HC machines. With the development of LSI fabrication technologies as the background, NSI is now feasible where a large-scale parallel processing system is installed on a wafer. The major problems in WSI are how to build in the required network structure on the planar structure wafer, and how to improve the yield by avoiding the defects generated in the fabrication process. In most of the past studies, the array (lattice) structure is employed in the realization of the network on NSI, and HC is seldom employed. In this paper sub-HC with 2p PEs is constructed as the row network (RN); and by connecting 2d-p RNs along the column direction, HC with 2d PEs is constructed. In other words, RN is constructed by the Diogenes method to compose an HC as a one-dimensional structure, and then the structure is extended to two dimensions by adding new switches and bus structures, resulting in a structure suited to WSI. Two structures are considered: the structure with redundant PE only in RN and the structure containing redundant RNs. A rough evaluation for the yield also is presented. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Systems & Computers in Japan is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1002/scj.4690220404
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 12
        StartPage: 29
    Subjects:
      – SubjectFull: Wafer-scale integration of circuits
        Type: general
      – SubjectFull: Systolic array circuits
        Type: general
      – SubjectFull: Hypercube networks (Computer networks)
        Type: general
      – SubjectFull: Parallel processing
        Type: general
      – SubjectFull: Computer architecture
        Type: general
      – SubjectFull: Computer systems
        Type: general
    Titles:
      – TitleFull: A Hypercube Design on Wafer-Scale Integration.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Ito, Hideo
      – PersonEntity:
          Name:
            NameFull: Suzuki, Nobuyuki
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 03
              Text: 3/1/91
              Type: published
              Y: 1991
          Identifiers:
            – Type: issn-print
              Value: 08821666
          Numbering:
            – Type: volume
              Value: 22
            – Type: issue
              Value: 4
          Titles:
            – TitleFull: Systems & Computers in Japan
              Type: main
ResultId 1