A Prolog Machine Based on VLSI Algorithms.

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Bibliographic Details
Title:	A Prolog Machine Based on VLSI Algorithms.
Authors:	Shobatake, Yasuro¹, Aiao, Rideo¹
Source:	Systems & Computers in Japan. Feb89, Vol. 20 Issue 2, p15-24. 10p.
Subjects:	Very large scale circuit integration, Systolic array circuits, Algorithms, Electronics, Transputers
Abstract:	This paper proposes a Prolog direct executer called PMV-2. to alleviate the von Neumann bottleneck, PMV-2 is provided with a number of processing elements, each of which stores a term symbol. Using the processing elements, the operations for terms can be executed in parallel. To simplify the algorithm for mapping the tree-structured data onto processing elements, data are represented by a format called symbol-line expression. Tree-structured data with this expression are mapped onto an array which has a straight-line arrangement I or processing elements. The configuration of the tree-structured data on the processing element array can be modified using the methods called Partial Global Commication and Partial Shift. To Implement a large number of processing elements, PMV-2 is constructed based on the VLSI algorithms. A performance evaluation has been made, revealing that the processing speed of approximately 450 kLips is obtained by PMV-2, which is nearly the same as that of a presently available high-speed Prolog system with a compiler. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	This paper proposes a Prolog direct executer called PMV-2. to alleviate the von Neumann bottleneck, PMV-2 is provided with a number of processing elements, each of which stores a term symbol. Using the processing elements, the operations for terms can be executed in parallel. To simplify the algorithm for mapping the tree-structured data onto processing elements, data are represented by a format called symbol-line expression. Tree-structured data with this expression are mapped onto an array which has a straight-line arrangement I or processing elements. The configuration of the tree-structured data on the processing element array can be modified using the methods called Partial Global Commication and Partial Shift. To Implement a large number of processing elements, PMV-2 is constructed based on the VLSI algorithms. A performance evaluation has been made, revealing that the processing speed of approximately 450 kLips is obtained by PMV-2, which is nearly the same as that of a presently available high-speed Prolog system with a compiler. [ABSTRACT FROM AUTHOR]
ISSN:	08821666
DOI:	10.1002/scj.4690200202