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A Prolog Machine Based on VLSI Algorithms.

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Title: A Prolog Machine Based on VLSI Algorithms.
Authors: Shobatake, Yasuro1, Aiao, Rideo1
Source: Systems & Computers in Japan. Feb89, Vol. 20 Issue 2, p15-24. 10p.
Subjects: Very large scale circuit integration, Systolic array circuits, Algorithms, Electronics, Transputers
Abstract: This paper proposes a Prolog direct executer called PMV-2. to alleviate the von Neumann bottleneck, PMV-2 is provided with a number of processing elements, each of which stores a term symbol. Using the processing elements, the operations for terms can be executed in parallel. To simplify the algorithm for mapping the tree-structured data onto processing elements, data are represented by a format called symbol-line expression. Tree-structured data with this expression are mapped onto an array which has a straight-line arrangement I or processing elements. The configuration of the tree-structured data on the processing element array can be modified using the methods called Partial Global Commication and Partial Shift. To Implement a large number of processing elements, PMV-2 is constructed based on the VLSI algorithms. A performance evaluation has been made, revealing that the processing speed of approximately 450 kLips is obtained by PMV-2, which is nearly the same as that of a presently available high-speed Prolog system with a compiler. [ABSTRACT FROM AUTHOR]
Copyright of Systems & Computers in Japan is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: A Prolog Machine Based on VLSI Algorithms.
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  Data: <searchLink fieldCode="DE" term="%22Very+large+scale+circuit+integration%22">Very large scale circuit integration</searchLink><br /><searchLink fieldCode="DE" term="%22Systolic+array+circuits%22">Systolic array circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Algorithms%22">Algorithms</searchLink><br /><searchLink fieldCode="DE" term="%22Electronics%22">Electronics</searchLink><br /><searchLink fieldCode="DE" term="%22Transputers%22">Transputers</searchLink>
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  Data: This paper proposes a Prolog direct executer called PMV-2. to alleviate the von Neumann bottleneck, PMV-2 is provided with a number of processing elements, each of which stores a term symbol. Using the processing elements, the operations for terms can be executed in parallel. To simplify the algorithm for mapping the tree-structured data onto processing elements, data are represented by a format called symbol-line expression. Tree-structured data with this expression are mapped onto an array which has a straight-line arrangement I or processing elements. The configuration of the tree-structured data on the processing element array can be modified using the methods called Partial Global Commication and Partial Shift. To Implement a large number of processing elements, PMV-2 is constructed based on the VLSI algorithms. A performance evaluation has been made, revealing that the processing speed of approximately 450 kLips is obtained by PMV-2, which is nearly the same as that of a presently available high-speed Prolog system with a compiler. [ABSTRACT FROM AUTHOR]
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  Data: <i>Copyright of Systems & Computers in Japan is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1002/scj.4690200202
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        Type: general
      – SubjectFull: Systolic array circuits
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      – SubjectFull: Algorithms
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      – SubjectFull: Electronics
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      – SubjectFull: Transputers
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              Text: Feb89
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              Y: 1989
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