Transparent Memory: A Hardware Solution to the Memory Conflict Problem.

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Bibliographic Details
Title:	Transparent Memory: A Hardware Solution to the Memory Conflict Problem.
Authors:	Hisano, Takumi¹
Source:	Systems & Computers in Japan. Nov86, Vol. 17 Issue 11, p100-108. 9p.
Subjects:	Ferroelectric RAM, Read-only memory, Simulation methods & models, Performance evaluation, Multiprocessors, Microprocessors
Abstract:	The paper proposes a memory organization aiming at reduction of memory conflict produced by the multiple access. The proposed memory organization has the effect of suppressing not only the memory conflicts but also the write memory conflicts. The conflict of read access is suppressed by using more than one memory module of the same content, and the conflict of write access is suppressed by restricting the write area and using the distributed communication mechanism. It is shown by the performance evaluation simulation that the memory conflict is sufficiently small compared with the number of multiple read memory and approaches a constant with the increase of the number of processors n. The hardware complexity is relatively large. The physical memory is n times compared with the logical address space and the number of memory control circuits is n². There is one connection between the memory control circuit and the connection network. By specifying the area of applications and simplifying the connection configuration, the hardware complexity can be reduced. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	The paper proposes a memory organization aiming at reduction of memory conflict produced by the multiple access. The proposed memory organization has the effect of suppressing not only the memory conflicts but also the write memory conflicts. The conflict of read access is suppressed by using more than one memory module of the same content, and the conflict of write access is suppressed by restricting the write area and using the distributed communication mechanism. It is shown by the performance evaluation simulation that the memory conflict is sufficiently small compared with the number of multiple read memory and approaches a constant with the increase of the number of processors n. The hardware complexity is relatively large. The physical memory is n times compared with the logical address space and the number of memory control circuits is n². There is one connection between the memory control circuit and the connection network. By specifying the area of applications and simplifying the connection configuration, the hardware complexity can be reduced. [ABSTRACT FROM AUTHOR]
ISSN:	08821666
DOI:	10.1002/scj.4690171110