Bibliographic Details
| Title: |
Downscaling of Floating-Gate EEPROM Modules for ASIC Applications. |
| Authors: |
Shiba, Kazuyoshi1, Kubota, Katsuhiko1 |
| Source: |
Electronics & Communications in Japan, Part 2: Electronics. Dec92, Vol. 75 Issue 12, p67-76. 10p. |
| Subjects: |
Integrated circuits, Read-only memory, Electronic circuits, Scaling laws (Statistical physics), Logic circuits, Computer circuits |
| Abstract: |
Downscaling methods of electrically erasable pros grammable ROM (EEPROM) for application-specific integrated circuit (ASIC) applications based on the double-poly floating-gate process were studied. Simple sealing of ASIC and EEPROM modules with the same scaling factor can significantly reduce the time for design and development. Horizontal scaling of the memory cell with unchanged vertical dimensions does not alter the cell performance because the capacitance coupling ratios are kept constant. Vertical scaling, which further reduces the cell size due to less short channel effects, requires the improvement in the tunnel oxide quality. For this purpose, an improved process also was studied in terms of process temperature and phosphorus concentration in polysilicon gate. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
