Fast ROM Macrocells for ASICs.

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Bibliographic Details
Title:	Fast ROM Macrocells for ASICs.
Authors:	Shibata, Nobutaro¹
Source:	Electronics & Communications in Japan, Part 2: Electronics. May96, Vol. 79 Issue 5, p77-87. 11p.
Subjects:	Read-only memory, Computer storage devices, Application-specific integrated circuits, Integrated circuits, Logic circuits, Digital electronics, Electronics
Abstract:	SRAMs and ROMs are installed on high-performance ASICs as the memory macrocells. This paper discusses the design of mask ROMs as the macrocells from the viewpoint of the high-speed and low-power dissipation. NOR-type memory cell array configuration is adopted, and the memory content is set using the LSI mask for contact process. A memory cell programming method is proposed where the source of the MOS transistor and the GND line are connected or disconnected according to the memory content. In this method, the adjacent cells can share the contact area to a bit-line. This helps to reduce the p-n junction capacitance, which dominates the parasitic capacitance of the bit-line, to be halved. Using a reference voltage generator, the bit-line is controlled close to GND level, which improves the detection sensitivity of the current-mirror sense amplifiers. The small-amplitude operation of the bit-lines is realized and the access time is reduced. As a technique to reduce the power dissipation, the virtual GND lines are introduced, which are controlled by the column address signals. The lines are controlled to the floating state in the stand-by mode so that the dynamic power dissipation is reduced. A test chip was designed and fabricated by a 0.5-μm CMOS process, and the address access time of 7.2 ns was obtained for the 4-K word x 4-bit organization. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	SRAMs and ROMs are installed on high-performance ASICs as the memory macrocells. This paper discusses the design of mask ROMs as the macrocells from the viewpoint of the high-speed and low-power dissipation. NOR-type memory cell array configuration is adopted, and the memory content is set using the LSI mask for contact process. A memory cell programming method is proposed where the source of the MOS transistor and the GND line are connected or disconnected according to the memory content. In this method, the adjacent cells can share the contact area to a bit-line. This helps to reduce the p-n junction capacitance, which dominates the parasitic capacitance of the bit-line, to be halved. Using a reference voltage generator, the bit-line is controlled close to GND level, which improves the detection sensitivity of the current-mirror sense amplifiers. The small-amplitude operation of the bit-lines is realized and the access time is reduced. As a technique to reduce the power dissipation, the virtual GND lines are introduced, which are controlled by the column address signals. The lines are controlled to the floating state in the stand-by mode so that the dynamic power dissipation is reduced. A test chip was designed and fabricated by a 0.5-μm CMOS process, and the address access time of 7.2 ns was obtained for the 4-K word x 4-bit organization. [ABSTRACT FROM AUTHOR]
ISSN:	8756663X
DOI:	10.1002/ecjb.4420790508