Fast ROM Macrocells for ASICs.
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| Title: | Fast ROM Macrocells for ASICs. |
|---|---|
| Authors: | Shibata, Nobutaro1 |
| Source: | Electronics & Communications in Japan, Part 2: Electronics. May96, Vol. 79 Issue 5, p77-87. 11p. |
| Subjects: | Read-only memory, Computer storage devices, Application-specific integrated circuits, Integrated circuits, Logic circuits, Digital electronics, Electronics |
| Abstract: | SRAMs and ROMs are installed on high-performance ASICs as the memory macrocells. This paper discusses the design of mask ROMs as the macrocells from the viewpoint of the high-speed and low-power dissipation. NOR-type memory cell array configuration is adopted, and the memory content is set using the LSI mask for contact process. A memory cell programming method is proposed where the source of the MOS transistor and the GND line are connected or disconnected according to the memory content. In this method, the adjacent cells can share the contact area to a bit-line. This helps to reduce the p-n junction capacitance, which dominates the parasitic capacitance of the bit-line, to be halved. Using a reference voltage generator, the bit-line is controlled close to GND level, which improves the detection sensitivity of the current-mirror sense amplifiers. The small-amplitude operation of the bit-lines is realized and the access time is reduced. As a technique to reduce the power dissipation, the virtual GND lines are introduced, which are controlled by the column address signals. The lines are controlled to the floating state in the stand-by mode so that the dynamic power dissipation is reduced. A test chip was designed and fabricated by a 0.5-μm CMOS process, and the address access time of 7.2 ns was obtained for the 4-K word x 4-bit organization. [ABSTRACT FROM AUTHOR] |
| Copyright of Electronics & Communications in Japan, Part 2: Electronics is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 14084135 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: Fast ROM Macrocells for ASICs. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Shibata%2C+Nobutaro%22">Shibata, Nobutaro</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Electronics+%26+Communications+in+Japan%2C+Part+2%3A+Electronics%22">Electronics & Communications in Japan, Part 2: Electronics</searchLink>. May96, Vol. 79 Issue 5, p77-87. 11p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Read-only+memory%22">Read-only memory</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+storage+devices%22">Computer storage devices</searchLink><br /><searchLink fieldCode="DE" term="%22Application-specific+integrated+circuits%22">Application-specific integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Logic+circuits%22">Logic circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+electronics%22">Digital electronics</searchLink><br /><searchLink fieldCode="DE" term="%22Electronics%22">Electronics</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: SRAMs and ROMs are installed on high-performance ASICs as the memory macrocells. This paper discusses the design of mask ROMs as the macrocells from the viewpoint of the high-speed and low-power dissipation. NOR-type memory cell array configuration is adopted, and the memory content is set using the LSI mask for contact process. A memory cell programming method is proposed where the source of the MOS transistor and the GND line are connected or disconnected according to the memory content. In this method, the adjacent cells can share the contact area to a bit-line. This helps to reduce the p-n junction capacitance, which dominates the parasitic capacitance of the bit-line, to be halved. Using a reference voltage generator, the bit-line is controlled close to GND level, which improves the detection sensitivity of the current-mirror sense amplifiers. The small-amplitude operation of the bit-lines is realized and the access time is reduced. As a technique to reduce the power dissipation, the virtual GND lines are introduced, which are controlled by the column address signals. The lines are controlled to the floating state in the stand-by mode so that the dynamic power dissipation is reduced. A test chip was designed and fabricated by a 0.5-μm CMOS process, and the address access time of 7.2 ns was obtained for the 4-K word x 4-bit organization. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Electronics & Communications in Japan, Part 2: Electronics is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1002/ecjb.4420790508 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 11 StartPage: 77 Subjects: – SubjectFull: Read-only memory Type: general – SubjectFull: Computer storage devices Type: general – SubjectFull: Application-specific integrated circuits Type: general – SubjectFull: Integrated circuits Type: general – SubjectFull: Logic circuits Type: general – SubjectFull: Digital electronics Type: general – SubjectFull: Electronics Type: general Titles: – TitleFull: Fast ROM Macrocells for ASICs. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Shibata, Nobutaro IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 05 Text: May96 Type: published Y: 1996 Identifiers: – Type: issn-print Value: 8756663X Numbering: – Type: volume Value: 79 – Type: issue Value: 5 Titles: – TitleFull: Electronics & Communications in Japan, Part 2: Electronics Type: main |
| ResultId | 1 |
