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DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy.

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Title: DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy.
Authors: Yarmand, Roohollah1 (AUTHOR) ryarmand@ut.ac.ir, Kamal, Mehdi1 (AUTHOR) mehdikamal@ut.ac.ir, Afzali-Kusha, Ali1 (AUTHOR) afzali@ut.ac.ir, Pedram, Massoud2 (AUTHOR) pedram@usc.edu
Source: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jan2020, Vol. 28 Issue 1, p273-286. 14p.
Subjects: Dynamic random access memory, Signal-to-noise ratio, Cache memory, Memory, Random access memory, Computer systems
Abstract: In this article, we propose a framework for determining approximation levels of approximable memories in a memory hierarchy for executing error resilient applications. The framework aims at optimizing the configuration for employing approximate memories in a computing system. It is based on considering data footprints at different memory hierarchy levels and an expected output quality to determine the amount of approximations at each memory hierarchy level. The problem of finding a suitable memory approximation configuration is performed using a branch-and-bound algorithm considering all possible memory approximation arrangements. The best configuration leading to the lowest power consumption when meeting the expected output quality is selected. The efficacy of the proposed framework for two memory hierarchies with different cache topologies is evaluated by comparing energy consumptions of approximate memories with those of the exact memory units in the memory hierarchy under different output accuracy level targets. For example, with 28 dB as a peak signal to noise ratio (PSNR) constraint, the study, which is performed for four image processing applications, indicates up to 54% and 22% power consumption improvements for the SRAM cache and the DRAM memory, respectively. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:In this article, we propose a framework for determining approximation levels of approximable memories in a memory hierarchy for executing error resilient applications. The framework aims at optimizing the configuration for employing approximate memories in a computing system. It is based on considering data footprints at different memory hierarchy levels and an expected output quality to determine the amount of approximations at each memory hierarchy level. The problem of finding a suitable memory approximation configuration is performed using a branch-and-bound algorithm considering all possible memory approximation arrangements. The best configuration leading to the lowest power consumption when meeting the expected output quality is selected. The efficacy of the proposed framework for two memory hierarchies with different cache topologies is evaluated by comparing energy consumptions of approximate memories with those of the exact memory units in the memory hierarchy under different output accuracy level targets. For example, with 28 dB as a peak signal to noise ratio (PSNR) constraint, the study, which is performed for four image processing applications, indicates up to 54% and 22% power consumption improvements for the SRAM cache and the DRAM memory, respectively. [ABSTRACT FROM AUTHOR]
ISSN:10638210
DOI:10.1109/TVLSI.2019.2935832