DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy.
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| Title: | DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy. |
|---|---|
| Authors: | Yarmand, Roohollah1 (AUTHOR) ryarmand@ut.ac.ir, Kamal, Mehdi1 (AUTHOR) mehdikamal@ut.ac.ir, Afzali-Kusha, Ali1 (AUTHOR) afzali@ut.ac.ir, Pedram, Massoud2 (AUTHOR) pedram@usc.edu |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Jan2020, Vol. 28 Issue 1, p273-286. 14p. |
| Subjects: | Dynamic random access memory, Signal-to-noise ratio, Cache memory, Memory, Random access memory, Computer systems |
| Abstract: | In this article, we propose a framework for determining approximation levels of approximable memories in a memory hierarchy for executing error resilient applications. The framework aims at optimizing the configuration for employing approximate memories in a computing system. It is based on considering data footprints at different memory hierarchy levels and an expected output quality to determine the amount of approximations at each memory hierarchy level. The problem of finding a suitable memory approximation configuration is performed using a branch-and-bound algorithm considering all possible memory approximation arrangements. The best configuration leading to the lowest power consumption when meeting the expected output quality is selected. The efficacy of the proposed framework for two memory hierarchies with different cache topologies is evaluated by comparing energy consumptions of approximate memories with those of the exact memory units in the memory hierarchy under different output accuracy level targets. For example, with 28 dB as a peak signal to noise ratio (PSNR) constraint, the study, which is performed for four image processing applications, indicates up to 54% and 22% power consumption improvements for the SRAM cache and the DRAM memory, respectively. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 141081680 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Yarmand%2C+Roohollah%22">Yarmand, Roohollah</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> ryarmand@ut.ac.ir</i><br /><searchLink fieldCode="AR" term="%22Kamal%2C+Mehdi%22">Kamal, Mehdi</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> mehdikamal@ut.ac.ir</i><br /><searchLink fieldCode="AR" term="%22Afzali-Kusha%2C+Ali%22">Afzali-Kusha, Ali</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> afzali@ut.ac.ir</i><br /><searchLink fieldCode="AR" term="%22Pedram%2C+Massoud%22">Pedram, Massoud</searchLink><relatesTo>2</relatesTo> (AUTHOR)<i> pedram@usc.edu</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Very+Large+Scale+Integration+%28VLSI%29+Systems%22">IEEE Transactions on Very Large Scale Integration (VLSI) Systems</searchLink>. Jan2020, Vol. 28 Issue 1, p273-286. 14p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Dynamic+random+access+memory%22">Dynamic random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Signal-to-noise+ratio%22">Signal-to-noise ratio</searchLink><br /><searchLink fieldCode="DE" term="%22Cache+memory%22">Cache memory</searchLink><br /><searchLink fieldCode="DE" term="%22Memory%22">Memory</searchLink><br /><searchLink fieldCode="DE" term="%22Random+access+memory%22">Random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+systems%22">Computer systems</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: In this article, we propose a framework for determining approximation levels of approximable memories in a memory hierarchy for executing error resilient applications. The framework aims at optimizing the configuration for employing approximate memories in a computing system. It is based on considering data footprints at different memory hierarchy levels and an expected output quality to determine the amount of approximations at each memory hierarchy level. The problem of finding a suitable memory approximation configuration is performed using a branch-and-bound algorithm considering all possible memory approximation arrangements. The best configuration leading to the lowest power consumption when meeting the expected output quality is selected. The efficacy of the proposed framework for two memory hierarchies with different cache topologies is evaluated by comparing energy consumptions of approximate memories with those of the exact memory units in the memory hierarchy under different output accuracy level targets. For example, with 28 dB as a peak signal to noise ratio (PSNR) constraint, the study, which is performed for four image processing applications, indicates up to 54% and 22% power consumption improvements for the SRAM cache and the DRAM memory, respectively. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2019.2935832 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 273 Subjects: – SubjectFull: Dynamic random access memory Type: general – SubjectFull: Signal-to-noise ratio Type: general – SubjectFull: Cache memory Type: general – SubjectFull: Memory Type: general – SubjectFull: Random access memory Type: general – SubjectFull: Computer systems Type: general Titles: – TitleFull: DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Yarmand, Roohollah – PersonEntity: Name: NameFull: Kamal, Mehdi – PersonEntity: Name: NameFull: Afzali-Kusha, Ali – PersonEntity: Name: NameFull: Pedram, Massoud IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: Jan2020 Type: published Y: 2020 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 28 – Type: issue Value: 1 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
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