A Fast Processor for 3-D Device Simulation Using Systolic Arrays.

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Bibliographic Details
Title:	A Fast Processor for 3-D Device Simulation Using Systolic Arrays.
Authors:	Naritomi, Takashi¹, Aso, Hirotomo¹, Kimura, Masayuki¹
Source:	Systems & Computers in Japan. 1/1/91, Vol. 22 Issue 1, p39-48. 10p.
Subjects:	Systolic array circuits, Wafer-scale integration of circuits, Very large scale circuit integration, Semiconductors, Parallel processing, Electronic data processing
Abstract:	To analyze the behavior of semiconductor devices numerically, we need to solve extremely large and sparse linear systems of equations as fast as possible. In this paper, parallel processing architectures using systolic arrays are proposed as a rapid solver of linear equations. The architectures are designed to reduce the number of processing elements, utilizing the regularity and the sparseness of coefficient matrices. The proposed systolic arrays consist of sixty-four cells for incomplete matrix decomposition and of seven cells for matrix-vector multiplication. This number is independent from the number N of grid points discretized for a three-dimensional device. The processing time of the array to solve a system of equations is proportional to N. Furthermore, the architectures are revised for faster parallel computation. The acceleration is based on the fact that a coefficient matrix is decomposed of smaller matrices. By the acceleration for matrix-vector multiplication, required cells are 8 x N2/3, but the processing time is proportional to N2/3. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	To analyze the behavior of semiconductor devices numerically, we need to solve extremely large and sparse linear systems of equations as fast as possible. In this paper, parallel processing architectures using systolic arrays are proposed as a rapid solver of linear equations. The architectures are designed to reduce the number of processing elements, utilizing the regularity and the sparseness of coefficient matrices. The proposed systolic arrays consist of sixty-four cells for incomplete matrix decomposition and of seven cells for matrix-vector multiplication. This number is independent from the number N of grid points discretized for a three-dimensional device. The processing time of the array to solve a system of equations is proportional to N. Furthermore, the architectures are revised for faster parallel computation. The acceleration is based on the fact that a coefficient matrix is decomposed of smaller matrices. By the acceleration for matrix-vector multiplication, required cells are 8 x N2/3, but the processing time is proportional to N2/3. [ABSTRACT FROM AUTHOR]
ISSN:	08821666
DOI:	10.1002/scj.4690220105