A Fast Processor for 3-D Device Simulation Using Systolic Arrays.
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| Title: | A Fast Processor for 3-D Device Simulation Using Systolic Arrays. |
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| Authors: | Naritomi, Takashi1, Aso, Hirotomo1, Kimura, Masayuki1 |
| Source: | Systems & Computers in Japan. 1/1/91, Vol. 22 Issue 1, p39-48. 10p. |
| Subjects: | Systolic array circuits, Wafer-scale integration of circuits, Very large scale circuit integration, Semiconductors, Parallel processing, Electronic data processing |
| Abstract: | To analyze the behavior of semiconductor devices numerically, we need to solve extremely large and sparse linear systems of equations as fast as possible. In this paper, parallel processing architectures using systolic arrays are proposed as a rapid solver of linear equations. The architectures are designed to reduce the number of processing elements, utilizing the regularity and the sparseness of coefficient matrices. The proposed systolic arrays consist of sixty-four cells for incomplete matrix decomposition and of seven cells for matrix-vector multiplication. This number is independent from the number N of grid points discretized for a three-dimensional device. The processing time of the array to solve a system of equations is proportional to N. Furthermore, the architectures are revised for faster parallel computation. The acceleration is based on the fact that a coefficient matrix is decomposed of smaller matrices. By the acceleration for matrix-vector multiplication, required cells are 8 x N2/3, but the processing time is proportional to N2/3. [ABSTRACT FROM AUTHOR] |
| Copyright of Systems & Computers in Japan is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 14130210 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: A Fast Processor for 3-D Device Simulation Using Systolic Arrays. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Naritomi%2C+Takashi%22">Naritomi, Takashi</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Aso%2C+Hirotomo%22">Aso, Hirotomo</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22Kimura%2C+Masayuki%22">Kimura, Masayuki</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Systems+%26+Computers+in+Japan%22">Systems & Computers in Japan</searchLink>. 1/1/91, Vol. 22 Issue 1, p39-48. 10p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Systolic+array+circuits%22">Systolic array circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Wafer-scale+integration+of+circuits%22">Wafer-scale integration of circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Very+large+scale+circuit+integration%22">Very large scale circuit integration</searchLink><br /><searchLink fieldCode="DE" term="%22Semiconductors%22">Semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Parallel+processing%22">Parallel processing</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+data+processing%22">Electronic data processing</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: To analyze the behavior of semiconductor devices numerically, we need to solve extremely large and sparse linear systems of equations as fast as possible. In this paper, parallel processing architectures using systolic arrays are proposed as a rapid solver of linear equations. The architectures are designed to reduce the number of processing elements, utilizing the regularity and the sparseness of coefficient matrices. The proposed systolic arrays consist of sixty-four cells for incomplete matrix decomposition and of seven cells for matrix-vector multiplication. This number is independent from the number N of grid points discretized for a three-dimensional device. The processing time of the array to solve a system of equations is proportional to N. Furthermore, the architectures are revised for faster parallel computation. The acceleration is based on the fact that a coefficient matrix is decomposed of smaller matrices. By the acceleration for matrix-vector multiplication, required cells are 8 x N2/3, but the processing time is proportional to N2/3. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Systems & Computers in Japan is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1002/scj.4690220105 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 10 StartPage: 39 Subjects: – SubjectFull: Systolic array circuits Type: general – SubjectFull: Wafer-scale integration of circuits Type: general – SubjectFull: Very large scale circuit integration Type: general – SubjectFull: Semiconductors Type: general – SubjectFull: Parallel processing Type: general – SubjectFull: Electronic data processing Type: general Titles: – TitleFull: A Fast Processor for 3-D Device Simulation Using Systolic Arrays. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Naritomi, Takashi – PersonEntity: Name: NameFull: Aso, Hirotomo – PersonEntity: Name: NameFull: Kimura, Masayuki IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Text: 1/1/91 Type: published Y: 1991 Identifiers: – Type: issn-print Value: 08821666 Numbering: – Type: volume Value: 22 – Type: issue Value: 1 Titles: – TitleFull: Systems & Computers in Japan Type: main |
| ResultId | 1 |
