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Current-Aware Flash Scheduling for Current Capping in Solid State Disks.

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Title: Current-Aware Flash Scheduling for Current Capping in Solid State Disks.
Authors: Chang, Li-Pin1 lpchang@cs.nctu.edu.tw, Cheng, Chia-Hsiang1 uj200380710@gmail.com, Chang, Shu-Ting1 sakura71410@gmail.com, Chou, Po-Han1 charliechou1010@gmail.com
Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Feb2020, Vol. 39 Issue 2, p321-334. 14p.
Subjects: Solid state drives, Electric power, Computer firmware, Systems software, Units of time
Abstract: Solid state disks (SSDs) employ internal parallelism to boost their input/output (I/O) performance, but a high degree of flash parallelism inevitably consumes a high level of current. To budget power or support multiple power sources, system software may force an SSD into a new power mode that has a specific current supply limit. This paper introduces a firmware approach to optimize SSD internal parallelism subject to a current supply limit. The proposed method involves two steps. First, we constructed current models of flash operations on the basis of real-world measurement results. Second, we designed a firmware scheduler to determine the actual starting time of each flash operation. The proposed scheduler accounted for flash aging, process variation, and internal resource contention, and it avoided any current cap violation by checking a few time points instead of every unit of time. Our experimental results indicated that the proposed approach outperformed existing methods with respect to I/O response time and throughput under realistic workloads. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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PubType: Academic Journal
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  Data: Current-Aware Flash Scheduling for Current Capping in Solid State Disks.
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  Data: <searchLink fieldCode="AR" term="%22Chang%2C+Li-Pin%22">Chang, Li-Pin</searchLink><relatesTo>1</relatesTo><i> lpchang@cs.nctu.edu.tw</i><br /><searchLink fieldCode="AR" term="%22Cheng%2C+Chia-Hsiang%22">Cheng, Chia-Hsiang</searchLink><relatesTo>1</relatesTo><i> uj200380710@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Chang%2C+Shu-Ting%22">Chang, Shu-Ting</searchLink><relatesTo>1</relatesTo><i> sakura71410@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Chou%2C+Po-Han%22">Chou, Po-Han</searchLink><relatesTo>1</relatesTo><i> charliechou1010@gmail.com</i>
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  Data: <searchLink fieldCode="DE" term="%22Solid+state+drives%22">Solid state drives</searchLink><br /><searchLink fieldCode="DE" term="%22Electric+power%22">Electric power</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+firmware%22">Computer firmware</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+software%22">Systems software</searchLink><br /><searchLink fieldCode="DE" term="%22Units+of+time%22">Units of time</searchLink>
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  Data: Solid state disks (SSDs) employ internal parallelism to boost their input/output (I/O) performance, but a high degree of flash parallelism inevitably consumes a high level of current. To budget power or support multiple power sources, system software may force an SSD into a new power mode that has a specific current supply limit. This paper introduces a firmware approach to optimize SSD internal parallelism subject to a current supply limit. The proposed method involves two steps. First, we constructed current models of flash operations on the basis of real-world measurement results. Second, we designed a firmware scheduler to determine the actual starting time of each flash operation. The proposed scheduler accounted for flash aging, process variation, and internal resource contention, and it avoided any current cap violation by checking a few time points instead of every unit of time. Our experimental results indicated that the proposed approach outperformed existing methods with respect to I/O response time and throughput under realistic workloads. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
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  Data: <i>Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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      – Type: doi
        Value: 10.1109/TCAD.2018.2887046
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      – Code: eng
        Text: English
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      – SubjectFull: Solid state drives
        Type: general
      – SubjectFull: Electric power
        Type: general
      – SubjectFull: Computer firmware
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      – SubjectFull: Systems software
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      – SubjectFull: Units of time
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            NameFull: Chang, Shu-Ting
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              Text: Feb2020
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              Y: 2020
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