Designing of a high speed, compact and low power, balanced-input balanced-output preamplifier latch based comparator.

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Bibliographic Details
Title:	Designing of a high speed, compact and low power, balanced-input balanced-output preamplifier latch based comparator.
Authors:	Ning Chen¹ ningchen3461@163.com, Man Zhang¹ manzhang1128@163.com
Source:	Journal of Vibroengineering. Dec2020, Vol. 22 Issue 8, p1847-1858. 12p.
Subjects:	Preamplifiers, Comparator circuits, Successive approximation analog-to-digital converters, Analog-to-digital converters
Abstract:	Analog and digital converters (ADCs) are the most inevitable part of today's high-speed human interacted devices. Continuous efforts are being made to improve their performance. Despite working for the improvement of whole ADC, efforts to improve sub-modules are also significant. Comparators are also a vital part of ADC. In this work, we have proposed a novel high-speed Balanced-Input Balanced-Output (BIBO) preamplifier latch based comparator design, to be used for the designing of an Asynchronous Successive Approximation Resister (SAR) ADC. In order to make comparison faster, we have employed Preamplifier-Latch based comparator. Transistor fingering is used to save area and makes large transistor easy to handle without changing their aspect ratio. We have implemented this latch using two back to back connected inverters. These inverters are farming a positive feedback arrangement that also prohibits the comparator from bursting into the oscillation. Latch circuit uses three non-overlapping phases namely phi1, phi2 and phi3 and dissipates less power when operated on a single 1V supply voltage. All these features collectively made this comparator expedient and obtained results confirm that it can be used effectively for the designing of SAR ADC. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	Analog and digital converters (ADCs) are the most inevitable part of today's high-speed human interacted devices. Continuous efforts are being made to improve their performance. Despite working for the improvement of whole ADC, efforts to improve sub-modules are also significant. Comparators are also a vital part of ADC. In this work, we have proposed a novel high-speed Balanced-Input Balanced-Output (BIBO) preamplifier latch based comparator design, to be used for the designing of an Asynchronous Successive Approximation Resister (SAR) ADC. In order to make comparison faster, we have employed Preamplifier-Latch based comparator. Transistor fingering is used to save area and makes large transistor easy to handle without changing their aspect ratio. We have implemented this latch using two back to back connected inverters. These inverters are farming a positive feedback arrangement that also prohibits the comparator from bursting into the oscillation. Latch circuit uses three non-overlapping phases namely phi1, phi2 and phi3 and dissipates less power when operated on a single 1V supply voltage. All these features collectively made this comparator expedient and obtained results confirm that it can be used effectively for the designing of SAR ADC. [ABSTRACT FROM AUTHOR]
ISSN:	13928716
DOI:	10.21595/jve.2020.21485