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Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems.

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Bibliographic Details
Title: Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems.
Authors: Kuttappa, Ragh1 (AUTHOR) fr67@drexel.edu, Taskin, Baris1 (AUTHOR) taskin@coe.drexel.edu, Lerner, Scott1 (AUTHOR) spl29@drexel.edu, Pano, Vasil1 (AUTHOR) vp93@drexel.edu
Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Apr2021, Vol. 68 Issue 4, p1636-1645. 10p.
Subjects: Synchronization, Silicon
Abstract: This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps. [ABSTRACT FROM AUTHOR]
ISSN:15498328
DOI:10.1109/TCSI.2021.3059228