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Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems.

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Title: Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems.
Authors: Kuttappa, Ragh1 (AUTHOR) fr67@drexel.edu, Taskin, Baris1 (AUTHOR) taskin@coe.drexel.edu, Lerner, Scott1 (AUTHOR) spl29@drexel.edu, Pano, Vasil1 (AUTHOR) vp93@drexel.edu
Source: IEEE Transactions on Circuits & Systems. Part I: Regular Papers. Apr2021, Vol. 68 Issue 4, p1636-1645. 10p.
Subjects: Synchronization, Silicon
Abstract: This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 149121986
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  Data: Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems.
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  Data: <searchLink fieldCode="AR" term="%22Kuttappa%2C+Ragh%22">Kuttappa, Ragh</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> fr67@drexel.edu</i><br /><searchLink fieldCode="AR" term="%22Taskin%2C+Baris%22">Taskin, Baris</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> taskin@coe.drexel.edu</i><br /><searchLink fieldCode="AR" term="%22Lerner%2C+Scott%22">Lerner, Scott</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> spl29@drexel.edu</i><br /><searchLink fieldCode="AR" term="%22Pano%2C+Vasil%22">Pano, Vasil</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> vp93@drexel.edu</i>
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  Data: <searchLink fieldCode="JN" term="%22IEEE+Transactions+on+Circuits+%26+Systems%2E+Part+I%3A+Regular+Papers%22">IEEE Transactions on Circuits & Systems. Part I: Regular Papers</searchLink>. Apr2021, Vol. 68 Issue 4, p1636-1645. 10p.
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  Data: This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
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  Data: <i>Copyright of IEEE Transactions on Circuits & Systems. Part I: Regular Papers is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/TCSI.2021.3059228
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      – Code: eng
        Text: English
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        PageCount: 10
        StartPage: 1636
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      – SubjectFull: Synchronization
        Type: general
      – SubjectFull: Silicon
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      – TitleFull: Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems.
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              M: 04
              Text: Apr2021
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              Y: 2021
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            – TitleFull: IEEE Transactions on Circuits & Systems. Part I: Regular Papers
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