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InGaAs-InP DHBTs for Increased Digital IC Bandwidth Having a 391-GHz fτ and 505-GHz fmax.

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Bibliographic Details
Title: InGaAs-InP DHBTs for Increased Digital IC Bandwidth Having a 391-GHz fτ and 505-GHz fmax.
Authors: Griffith, Z.1 griffith@ece.ucsb.edu, Dahlström, M.2, Rodwell, M. J. W.1, Fang, X.-M.3, Lubyshev, D.3, Wu, Y.3, Fastenau, J. M.3, Liu, W. K.3
Source: IEEE Electron Device Letters. Jan2005, Vol. 26 Issue 1, p11-13. 3p. 2 Diagrams, 6 Graphs.
Subjects: Bipolar transistors, Heterojunctions, Electric circuits, Digital electronics, Gallium arsenide semiconductors, Semiconductors, Semiconductor doping
Abstract: InP-In0.53Ga0.47As-InP double heterojunction bipolar transistors (DHBT) have been designed for use in high bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 391-GHz fτ and 505-GHz fmax, which is the highest fτ reported for an InP DHBT—as well as the highest simultaneous fτ and fmax for any mesa HBT. The devices have been aggressively scaled laterally for reduced base-collector capacitance Ccb. In addition, the base sheet resistance ρs along with the base and emitter contact resistivities ρc have been lowered. The dc current gain β is ≈36 and VBR,CEO = 5.1 V. The devices reported here employ a 30-nm highly doped InGaAs base, and a 150-nm collector containing an InGaAs-InAlAs superlattice grade at the base-collector junction. From this device design we also report a 142-GHz static frequency divider (a digital figure of merit for a device technology) fabricated on the same wafer. The divider operation is fully static, operating from fclk = 3 to 142.0 GHz while dissipating ≈ 800 mW of power in the circuit core. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies >100 GHz. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:InP-In0.53Ga0.47As-InP double heterojunction bipolar transistors (DHBT) have been designed for use in high bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 391-GHz fτ and 505-GHz fmax, which is the highest fτ reported for an InP DHBT—as well as the highest simultaneous fτ and fmax for any mesa HBT. The devices have been aggressively scaled laterally for reduced base-collector capacitance Ccb. In addition, the base sheet resistance ρs along with the base and emitter contact resistivities ρc have been lowered. The dc current gain β is ≈36 and VBR,CEO = 5.1 V. The devices reported here employ a 30-nm highly doped InGaAs base, and a 150-nm collector containing an InGaAs-InAlAs superlattice grade at the base-collector junction. From this device design we also report a 142-GHz static frequency divider (a digital figure of merit for a device technology) fabricated on the same wafer. The divider operation is fully static, operating from fclk = 3 to 142.0 GHz while dissipating ≈ 800 mW of power in the circuit core. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies >100 GHz. [ABSTRACT FROM AUTHOR]
ISSN:07413106
DOI:10.1109/LED.2004.840715