Temperature Analysis of a Dopingless TFET Considering Interface Trap Charges for Enhanced Reliability.
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| Title: | Temperature Analysis of a Dopingless TFET Considering Interface Trap Charges for Enhanced Reliability. |
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| Authors: | Sharma, Suruchi1 sharma.suru91@gmail.com, Basu, Rikmantra1 rikmantrabasu@nitdelhi.ac.in, Kaur, Baljit1 baljitkaur@nitdelhi.ac.in |
| Source: | IEEE Transactions on Electron Devices. May2022, Vol. 69 Issue 5, p2692-2697. 6p. |
| Subjects: | Tunnel field-effect transistors, Semiconductor materials, High temperatures, Threshold voltage, Metal oxide semiconductor field-effect transistors, Temperature |
| Abstract: | The dopingless tunnel field-effect transistors (DLTFETs) are captivating researchers over conventional TFETs as the former eliminates fabrication-related challenges such as random dopant fluctuations, requisite high thermal budget, and expensive annealing techniques, along with providing benefits of conventional TFET such as extremely low OFF-state current (${I}_{\mathrm{\scriptscriptstyle OFF}} $), less than 60-mV/dec average subthreshold swing, and immunity toward short-channel effects. However, DLTFET also faces challenges of low ON-state current (${I}_{\mathrm{\scriptscriptstyle ON}} $) and variation in electrical characteristics with temperature as bandgap of semiconductor material varies with temperature. So, in this article, we investigate the temperature-associated variations of Si/Ge heterojunction asymmetric-double-gate DLTFET (HJ-ADG-DLTFET) under the influence of interface trap charges (ITCs) for reliability assessment. This is done by investigating the effect of ITC along with temperature variations from 200 to 500 K, on analog/RF and linear performance metrics via simulations using Silvaco ATLAS. It is found that the Shockley–Read–Hall (SRH) phenomenon dominates at lower gate bias, resulting in ${I}_{\mathrm{\scriptscriptstyle OFF}} $ degradation at elevated temperatures. However, band-to-band tunneling (BTBT) phenomenon is prevalent at large gate voltage, which is weakly dependent on variations in temperature. Accordingly, at high temperatures, ${I}_{\mathrm{\scriptscriptstyle OFF}} $ is deteriorated by an order of 105, that is, increases from 10−17 A (200 K) to 10−12 A (500 K). Also, at high temperatures, the reduction in threshold voltage (${V}_{\text {th}} $) and delay ($\tau $) and, increment in cut-off frequency (${f}_{T} $) is observed, causing up-gradation in device performance. Furthermore, the impact of source–gate length (${L}_{\text {GAP},{S}} $), drain–gate length (${L}_{\text {GAP},{D}} $), and semiconductor body thickness (${T}_{\text {Si}} $) variations are also investigated. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
| Abstract: | The dopingless tunnel field-effect transistors (DLTFETs) are captivating researchers over conventional TFETs as the former eliminates fabrication-related challenges such as random dopant fluctuations, requisite high thermal budget, and expensive annealing techniques, along with providing benefits of conventional TFET such as extremely low OFF-state current (${I}_{\mathrm{\scriptscriptstyle OFF}} $), less than 60-mV/dec average subthreshold swing, and immunity toward short-channel effects. However, DLTFET also faces challenges of low ON-state current (${I}_{\mathrm{\scriptscriptstyle ON}} $) and variation in electrical characteristics with temperature as bandgap of semiconductor material varies with temperature. So, in this article, we investigate the temperature-associated variations of Si/Ge heterojunction asymmetric-double-gate DLTFET (HJ-ADG-DLTFET) under the influence of interface trap charges (ITCs) for reliability assessment. This is done by investigating the effect of ITC along with temperature variations from 200 to 500 K, on analog/RF and linear performance metrics via simulations using Silvaco ATLAS. It is found that the Shockley–Read–Hall (SRH) phenomenon dominates at lower gate bias, resulting in ${I}_{\mathrm{\scriptscriptstyle OFF}} $ degradation at elevated temperatures. However, band-to-band tunneling (BTBT) phenomenon is prevalent at large gate voltage, which is weakly dependent on variations in temperature. Accordingly, at high temperatures, ${I}_{\mathrm{\scriptscriptstyle OFF}} $ is deteriorated by an order of 105, that is, increases from 10−17 A (200 K) to 10−12 A (500 K). Also, at high temperatures, the reduction in threshold voltage (${V}_{\text {th}} $) and delay ($\tau $) and, increment in cut-off frequency (${f}_{T} $) is observed, causing up-gradation in device performance. Furthermore, the impact of source–gate length (${L}_{\text {GAP},{S}} $), drain–gate length (${L}_{\text {GAP},{D}} $), and semiconductor body thickness (${T}_{\text {Si}} $) variations are also investigated. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 00189383 |
| DOI: | 10.1109/TED.2022.3156895 |
