Bibliographic Details
| Title: |
Capacitor-Less 4F DRAM Using Vertical InGaAs Junction for Ultimate Cell Scalability. |
| Authors: |
Kim, Joon Pyo1 (AUTHOR), Sim, Jaeho1 (AUTHOR), Bidenko, Pavlo1 (AUTHOR), Geum, Dae-Myeong1 (AUTHOR), Kim, Seong Kwang1 (AUTHOR), Shim, Joonsup1 (AUTHOR), Kim, Jongmin2 (AUTHOR) jongmin.kim@kanc.re.kr, Kim, Sanghyeon1 (AUTHOR) shkim.ee@kaist.ac.kr |
| Source: |
IEEE Electron Device Letters. Nov2022, Vol. 43 Issue 11, p1834-1837. 4p. |
| Subjects: |
Cell junctions, Indium gallium arsenide, Scalability, Impact ionization, Temporoparietal junction, Random access memory |
| Abstract: |
In this work, we demonstrated capacitor-less 4F2 2-terminal InGaAs npn junction DRAM through careful device design. Using epitaxially grown InGaAs which have a steep junction, fabricated InGaAs bistable resistor (biristor) DRAM showed low voltage operation (~2 V), fast switching speed (<20 ns), long-term retention (103 s at 85 °C), and high endurance (>1010 cycles) with a high sensing margin. Considering this feasibility study, we believe that InGaAs $\text{n}^{+}$ pn+ junction DRAM could be a good technological option for future scalable 3D DRAM. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
