VHDL implementation of circular shifting‐partial transmit sequence in MIMO OFDM systems.
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| Title: | VHDL implementation of circular shifting‐partial transmit sequence in MIMO OFDM systems. |
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| Authors: | Abdel‐Atty, Heba M.1 (AUTHOR), Hassaneen, Saly S.1 (AUTHOR), Soliman, Heba Y.1 (AUTHOR) hebayms1@yahoo.com |
| Source: | International Journal of Communication Systems. Feb2023, Vol. 36 Issue 3, p1-22. 22p. |
| Subjects: | VHDL (Computer hardware description language), MIMO systems, Field programmable gate arrays |
| Abstract: | Summary: One of the basic issues in orthogonal frequency‐division multiplexing (OFDM) frameworks is the peak‐to‐average power ratio (PAPR). There are several PAPR reduction methods available. The partial transmit sequence (PTS) technique is considered one of the superior techniques for overcoming this issue. In this study, an efficient VHSIC hardware description language VHDL implementation of the PTS design utilising roundabout circular shifting CS was planned. The proposed structured method was designed as a real‐time prototype circuit over a field programmable gate array (FPGA) utilising the VHDL language. The implementation results of the prototype circuit in terms of the resources used in the FPGA using the Xilinx synthesis tool on the Virtex‐5 board for SISO, 2 × 2 MIMO and 4 × 4 MIMO models for N‐IFFT 64 and 256 points are presented. The structured framework effectively combined to be a compact framework with low intricacy and high speed. Testing of the implemented circuit verified its functionality. A comparison of our proposed CS‐PTS scheme with previously used PTS schemes, such as the subblock scheme, showed that our proposed method is superior in terms of hardware complexity reduction. [ABSTRACT FROM AUTHOR] |
| Copyright of International Journal of Communication Systems is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Abstract: | Summary: One of the basic issues in orthogonal frequency‐division multiplexing (OFDM) frameworks is the peak‐to‐average power ratio (PAPR). There are several PAPR reduction methods available. The partial transmit sequence (PTS) technique is considered one of the superior techniques for overcoming this issue. In this study, an efficient VHSIC hardware description language VHDL implementation of the PTS design utilising roundabout circular shifting CS was planned. The proposed structured method was designed as a real‐time prototype circuit over a field programmable gate array (FPGA) utilising the VHDL language. The implementation results of the prototype circuit in terms of the resources used in the FPGA using the Xilinx synthesis tool on the Virtex‐5 board for SISO, 2 × 2 MIMO and 4 × 4 MIMO models for N‐IFFT 64 and 256 points are presented. The structured framework effectively combined to be a compact framework with low intricacy and high speed. Testing of the implemented circuit verified its functionality. A comparison of our proposed CS‐PTS scheme with previously used PTS schemes, such as the subblock scheme, showed that our proposed method is superior in terms of hardware complexity reduction. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 10745351 |
| DOI: | 10.1002/dac.5386 |
