Bibliographic Details
| Title: |
Bit-level systolic imlementation of 1-D and 2-D discrete wavelet transform. |
| Authors: |
Nayak, S. S.1 |
| Source: |
IEE Proceedings -- Circuits, Devices & Systems. Feb2005, Vol. 152 Issue 1, p25-32. 8p. |
| Subjects: |
Systolic array circuits, Wavelets (Mathematics), Algorithms, Computer arithmetic |
| Abstract: |
Presents the systolic array architecture for VSLI implementation of the one-dimensional discrete wavelet transform. Computation of both high and low pass frequency coefficients in the same clock cycle; Representation of the arbitrary square integrable function; Determination of the decomposition algorithm. |
| Database: |
Engineering Source |
