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Bit-level systolic imlementation of 1-D and 2-D discrete wavelet transform.

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Title: Bit-level systolic imlementation of 1-D and 2-D discrete wavelet transform.
Authors: Nayak, S. S.1
Source: IEE Proceedings -- Circuits, Devices & Systems. Feb2005, Vol. 152 Issue 1, p25-32. 8p.
Subjects: Systolic array circuits, Wavelets (Mathematics), Algorithms, Computer arithmetic
Abstract: Presents the systolic array architecture for VSLI implementation of the one-dimensional discrete wavelet transform. Computation of both high and low pass frequency coefficients in the same clock cycle; Representation of the arbitrary square integrable function; Determination of the decomposition algorithm.
Database: Engineering Source
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PubType: Academic Journal
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  Data: Bit-level systolic imlementation of 1-D and 2-D discrete wavelet transform.
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  Data: Presents the systolic array architecture for VSLI implementation of the one-dimensional discrete wavelet transform. Computation of both high and low pass frequency coefficients in the same clock cycle; Representation of the arbitrary square integrable function; Determination of the decomposition algorithm.
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=16575217
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        Value: 10.1049/ip-cds:20040745
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        Text: English
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      – SubjectFull: Systolic array circuits
        Type: general
      – SubjectFull: Wavelets (Mathematics)
        Type: general
      – SubjectFull: Algorithms
        Type: general
      – SubjectFull: Computer arithmetic
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      – TitleFull: Bit-level systolic imlementation of 1-D and 2-D discrete wavelet transform.
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              Text: Feb2005
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              Y: 2005
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