Bibliographic Details
| Title: |
DFT for Multi-Die Designs – The Way Forward. |
| Authors: |
Hutner, Mark, Butler, Ken |
| Source: |
Advancing Microelectronics. 2023, Vol. 50 Issue 2, p14-17. 4p. |
| Subjects: |
Test design |
| Abstract: |
Design scaling is driving large System-on-Chips (SoCs) towards disaggregation into smaller chiplet-based architectures. This substantially reduces design complexity, but it affects design for test (DFT). DFT implementation for chiplets needs to consider how such chiplets are integrated across multiple designs for varied usages. This paper discusses DFT for chiplets. It leverages techniques and methodologies used in two-dimensional (2D) monolithic designs, yet it describes how to comply with IEEE standards like 1149.1, 1500, 1687 and 1838. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
