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DFT for Multi-Die Designs – The Way Forward.

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Title: DFT for Multi-Die Designs – The Way Forward.
Authors: Hutner, Mark, Butler, Ken
Source: Advancing Microelectronics. 2023, Vol. 50 Issue 2, p14-17. 4p.
Subjects: Test design
Abstract: Design scaling is driving large System-on-Chips (SoCs) towards disaggregation into smaller chiplet-based architectures. This substantially reduces design complexity, but it affects design for test (DFT). DFT implementation for chiplets needs to consider how such chiplets are integrated across multiple designs for varied usages. This paper discusses DFT for chiplets. It leverages techniques and methodologies used in two-dimensional (2D) monolithic designs, yet it describes how to comply with IEEE standards like 1149.1, 1500, 1687 and 1838. [ABSTRACT FROM AUTHOR]
Copyright of Advancing Microelectronics is the property of International Microelectronics & Packaging Society and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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Header DbId: egs
DbLabel: Engineering Source
An: 169637200
AccessLevel: 6
PubType: Periodical
PubTypeId: serialPeriodical
PreciseRelevancyScore: 0
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: DFT for Multi-Die Designs – The Way Forward.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Hutner%2C+Mark%22">Hutner, Mark</searchLink><br /><searchLink fieldCode="AR" term="%22Butler%2C+Ken%22">Butler, Ken</searchLink>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Advancing+Microelectronics%22">Advancing Microelectronics</searchLink>. 2023, Vol. 50 Issue 2, p14-17. 4p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Test+design%22">Test design</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: Design scaling is driving large System-on-Chips (SoCs) towards disaggregation into smaller chiplet-based architectures. This substantially reduces design complexity, but it affects design for test (DFT). DFT implementation for chiplets needs to consider how such chiplets are integrated across multiple designs for varied usages. This paper discusses DFT for chiplets. It leverages techniques and methodologies used in two-dimensional (2D) monolithic designs, yet it describes how to comply with IEEE standards like 1149.1, 1500, 1687 and 1838. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Advancing Microelectronics is the property of International Microelectronics & Packaging Society and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
  BibEntity:
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 4
        StartPage: 14
    Subjects:
      – SubjectFull: Test design
        Type: general
    Titles:
      – TitleFull: DFT for Multi-Die Designs – The Way Forward.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Hutner, Mark
      – PersonEntity:
          Name:
            NameFull: Butler, Ken
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 03
              Text: 2023
              Type: published
              Y: 2023
          Identifiers:
            – Type: issn-print
              Value: 23807008
          Numbering:
            – Type: volume
              Value: 50
            – Type: issue
              Value: 2
          Titles:
            – TitleFull: Advancing Microelectronics
              Type: main
ResultId 1