A mini I2C bus interface circuit design and its VLSI implementation.
Saved in:
| Title: | A mini I2C bus interface circuit design and its VLSI implementation. |
|---|---|
| Authors: | Huang, Caixia1 (AUTHOR) Ken5cs@foxmail.com, Yang, Sen2 (AUTHOR) |
| Source: | Journal of Supercomputing. Nov2024, Vol. 80 Issue 16, p23794-23814. 21p. |
| Subjects: | Finite state machines, Interface circuits, Data transmission systems, Machine design, Very large scale circuit integration |
| Abstract: | The existing I2C interfaces require significant CPU intervention for data communication. In SOC systems, when using internally integrated I2C modules as masters, software control of I/O ports is necessary to emulate the I2C protocol for data transmission. This paper proposes a Mini I2C bus interface circuit design scheme that supports both master and slave modes. The I2C interface features minimal CPU intervention during data transmission, ease of use, small circuit area, and low power consumption. Additionally, the internal state machine design employs independent finite state machines (FSMs) for master and slave modes, enabling flexible configuration of the I2C module to operate in either mode. In comparison to reference (ShenZhen in Microelectronics Technology CO.BJ8M306A, Datasheet.2019.12.2., 2019), the proposed I2C solution reduces CPU instructions by 50% during data transmission, and by 33% compared to reference (GigaDevice Semiconductor Inc. GD32F1x0, Datasheet, 2022). After DC synthesis, the proposed design occupies only 14% of the area and consumes only 3.6% of the power of the Open Source I2C Design (Forencich in verilog-i2c. GitHub repository. Retrieved from https://github.com/alexforencich/verilog-i2c, n.d.). Therefore, this design scheme is better suited for low-power systems. The proposed design was validated through simulation using Xilinx ISE 14.7 with a SPARTAN 3 FPGA model xc3s500e-5pq208, and finally implemented using Huahong 95 nm CMOS technology, demonstrating high integration and low power consumption. [ABSTRACT FROM AUTHOR] |
| Copyright of Journal of Supercomputing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
|
Full text is not displayed to guests.
Login for full access.
|
|
| Abstract: | The existing I2C interfaces require significant CPU intervention for data communication. In SOC systems, when using internally integrated I2C modules as masters, software control of I/O ports is necessary to emulate the I2C protocol for data transmission. This paper proposes a Mini I2C bus interface circuit design scheme that supports both master and slave modes. The I2C interface features minimal CPU intervention during data transmission, ease of use, small circuit area, and low power consumption. Additionally, the internal state machine design employs independent finite state machines (FSMs) for master and slave modes, enabling flexible configuration of the I2C module to operate in either mode. In comparison to reference (ShenZhen in Microelectronics Technology CO.BJ8M306A, Datasheet.2019.12.2., 2019), the proposed I2C solution reduces CPU instructions by 50% during data transmission, and by 33% compared to reference (GigaDevice Semiconductor Inc. GD32F1x0, Datasheet, 2022). After DC synthesis, the proposed design occupies only 14% of the area and consumes only 3.6% of the power of the Open Source I2C Design (Forencich in verilog-i2c. GitHub repository. Retrieved from https://github.com/alexforencich/verilog-i2c, n.d.). Therefore, this design scheme is better suited for low-power systems. The proposed design was validated through simulation using Xilinx ISE 14.7 with a SPARTAN 3 FPGA model xc3s500e-5pq208, and finally implemented using Huahong 95 nm CMOS technology, demonstrating high integration and low power consumption. [ABSTRACT FROM AUTHOR] |
|---|---|
| ISSN: | 09208542 |
| DOI: | 10.1007/s11227-024-06370-9 |
