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Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs.

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Title: Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs.
Authors: Kareem, Husam1 (AUTHOR) hus_almagsoosi@edu.bme.hu, Dunaev, Dmitriy1 (AUTHOR)
Source: Integration: The VLSI Journal. Nov2024, Vol. 99, pN.PAG-N.PAG. 1p.
Subjects: Mathematical logic, Physical mobility, Electronic equipment, Entropy, Hardware
Abstract: In the field of hardware security, the physical unclonable function (PUF) is known as a significant advancement for its unique and unclonable outputs, serving as a 'digital fingerprint' for electronic devices. This distinctiveness is crucial for high-security tasks such as device authentication and cryptographic key generation. The PUF's input-output combinations, known as challenge-response pairs (CRPs), are essential to its functionality. Although the Ring Oscillator (RO) PUF is notable for its security advantages and straightforward implementation, it's considered a 'weak' PUF due to its limited CRPs, highlighting a demand for more robust and secure PUF designs. This paper introduces a novel configurable inversion unit (CIU), integrating two universal logic gates, NAND and NOR, to be utilized in building various configurable ring oscillator (CRO) PUF models. Using the newly proposed CIU, we introduce two distinct CRO-PUF configurations. The first one includes 16-ring oscillators, while the second has 8-ring oscillators. A modified version of this CIU is introduced to increase the size of CRPs that a PUF can handle. A comprehensive assessment process of these configurations underscores the superior performance of these models across various parameters, including reliability, distinctiveness, balance, bit-aliasing, and randomness. • MUX-based CRO PUFs mainly utilize inverters and XOR gates. • XOR gates in CRO-PUFs, with/without MUXs, boost RO-PUF efficacy. • Few CRO-PUF designs use NAND/NOR universal gates. • More ring oscillators in PUFs link to better security. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:In the field of hardware security, the physical unclonable function (PUF) is known as a significant advancement for its unique and unclonable outputs, serving as a 'digital fingerprint' for electronic devices. This distinctiveness is crucial for high-security tasks such as device authentication and cryptographic key generation. The PUF's input-output combinations, known as challenge-response pairs (CRPs), are essential to its functionality. Although the Ring Oscillator (RO) PUF is notable for its security advantages and straightforward implementation, it's considered a 'weak' PUF due to its limited CRPs, highlighting a demand for more robust and secure PUF designs. This paper introduces a novel configurable inversion unit (CIU), integrating two universal logic gates, NAND and NOR, to be utilized in building various configurable ring oscillator (CRO) PUF models. Using the newly proposed CIU, we introduce two distinct CRO-PUF configurations. The first one includes 16-ring oscillators, while the second has 8-ring oscillators. A modified version of this CIU is introduced to increase the size of CRPs that a PUF can handle. A comprehensive assessment process of these configurations underscores the superior performance of these models across various parameters, including reliability, distinctiveness, balance, bit-aliasing, and randomness. • MUX-based CRO PUFs mainly utilize inverters and XOR gates. • XOR gates in CRO-PUFs, with/without MUXs, boost RO-PUF efficacy. • Few CRO-PUF designs use NAND/NOR universal gates. • More ring oscillators in PUFs link to better security. [ABSTRACT FROM AUTHOR]
ISSN:01679260
DOI:10.1016/j.vlsi.2024.102257