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Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs.

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Title: Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs.
Authors: Kareem, Husam1 (AUTHOR) hus_almagsoosi@edu.bme.hu, Dunaev, Dmitriy1 (AUTHOR)
Source: Integration: The VLSI Journal. Nov2024, Vol. 99, pN.PAG-N.PAG. 1p.
Subjects: Mathematical logic, Physical mobility, Electronic equipment, Entropy, Hardware
Abstract: In the field of hardware security, the physical unclonable function (PUF) is known as a significant advancement for its unique and unclonable outputs, serving as a 'digital fingerprint' for electronic devices. This distinctiveness is crucial for high-security tasks such as device authentication and cryptographic key generation. The PUF's input-output combinations, known as challenge-response pairs (CRPs), are essential to its functionality. Although the Ring Oscillator (RO) PUF is notable for its security advantages and straightforward implementation, it's considered a 'weak' PUF due to its limited CRPs, highlighting a demand for more robust and secure PUF designs. This paper introduces a novel configurable inversion unit (CIU), integrating two universal logic gates, NAND and NOR, to be utilized in building various configurable ring oscillator (CRO) PUF models. Using the newly proposed CIU, we introduce two distinct CRO-PUF configurations. The first one includes 16-ring oscillators, while the second has 8-ring oscillators. A modified version of this CIU is introduced to increase the size of CRPs that a PUF can handle. A comprehensive assessment process of these configurations underscores the superior performance of these models across various parameters, including reliability, distinctiveness, balance, bit-aliasing, and randomness. • MUX-based CRO PUFs mainly utilize inverters and XOR gates. • XOR gates in CRO-PUFs, with/without MUXs, boost RO-PUF efficacy. • Few CRO-PUF designs use NAND/NOR universal gates. • More ring oscillators in PUFs link to better security. [ABSTRACT FROM AUTHOR]
Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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Header DbId: egs
DbLabel: Engineering Source
An: 179419531
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
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Items – Name: Title
  Label: Title
  Group: Ti
  Data: Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs.
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22Kareem%2C+Husam%22">Kareem, Husam</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> hus_almagsoosi@edu.bme.hu</i><br /><searchLink fieldCode="AR" term="%22Dunaev%2C+Dmitriy%22">Dunaev, Dmitriy</searchLink><relatesTo>1</relatesTo> (AUTHOR)
– Name: TitleSource
  Label: Source
  Group: Src
  Data: <searchLink fieldCode="JN" term="%22Integration%3A+The+VLSI+Journal%22">Integration: The VLSI Journal</searchLink>. Nov2024, Vol. 99, pN.PAG-N.PAG. 1p.
– Name: Subject
  Label: Subjects
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22Mathematical+logic%22">Mathematical logic</searchLink><br /><searchLink fieldCode="DE" term="%22Physical+mobility%22">Physical mobility</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+equipment%22">Electronic equipment</searchLink><br /><searchLink fieldCode="DE" term="%22Entropy%22">Entropy</searchLink><br /><searchLink fieldCode="DE" term="%22Hardware%22">Hardware</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: In the field of hardware security, the physical unclonable function (PUF) is known as a significant advancement for its unique and unclonable outputs, serving as a 'digital fingerprint' for electronic devices. This distinctiveness is crucial for high-security tasks such as device authentication and cryptographic key generation. The PUF's input-output combinations, known as challenge-response pairs (CRPs), are essential to its functionality. Although the Ring Oscillator (RO) PUF is notable for its security advantages and straightforward implementation, it's considered a 'weak' PUF due to its limited CRPs, highlighting a demand for more robust and secure PUF designs. This paper introduces a novel configurable inversion unit (CIU), integrating two universal logic gates, NAND and NOR, to be utilized in building various configurable ring oscillator (CRO) PUF models. Using the newly proposed CIU, we introduce two distinct CRO-PUF configurations. The first one includes 16-ring oscillators, while the second has 8-ring oscillators. A modified version of this CIU is introduced to increase the size of CRPs that a PUF can handle. A comprehensive assessment process of these configurations underscores the superior performance of these models across various parameters, including reliability, distinctiveness, balance, bit-aliasing, and randomness. • MUX-based CRO PUFs mainly utilize inverters and XOR gates. • XOR gates in CRO-PUFs, with/without MUXs, boost RO-PUF efficacy. • Few CRO-PUF designs use NAND/NOR universal gates. • More ring oscillators in PUFs link to better security. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Integration: The VLSI Journal is the property of Elsevier B.V. and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=egs&AN=179419531
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.1016/j.vlsi.2024.102257
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 1
        StartPage: N.PAG
    Subjects:
      – SubjectFull: Mathematical logic
        Type: general
      – SubjectFull: Physical mobility
        Type: general
      – SubjectFull: Electronic equipment
        Type: general
      – SubjectFull: Entropy
        Type: general
      – SubjectFull: Hardware
        Type: general
    Titles:
      – TitleFull: Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs.
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: Kareem, Husam
      – PersonEntity:
          Name:
            NameFull: Dunaev, Dmitriy
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 11
              Text: Nov2024
              Type: published
              Y: 2024
          Identifiers:
            – Type: issn-print
              Value: 01679260
          Numbering:
            – Type: volume
              Value: 99
          Titles:
            – TitleFull: Integration: The VLSI Journal
              Type: main
ResultId 1