Bibliographic Details
| Title: |
Optimization of memory access logic in BOOM processor. |
| Authors: |
ZHOU Lin-ning1 134409277@qq.com, LIU Jie1 liujie52@zjhu.edu.cn, LI Hong-kui1 ws_lhk01@163.com, FU Hao-dong1 594020439@qq.com, LIU Hong-hai1 204850763@qq.com, XIAO Hao1 :xiaohao@zjhu.edu.cn |
| Source: |
Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Aug2024, Vol. 46 Issue 8, p1390-1394. 5p. |
| Abstract: |
Although the Store instruction backtracking strategy adopted by BOOM processors solves the problem of data conflicts caused by out-of-order execution of memory access instructions, this strategy can lead to a large amount of pipeline flushing and reduce the processor performance. To address this, a correlation prediction method for memory access instructions is proposed. This method cancels the query operation before the Load instruction accesses memory and adds a Load instruction correlation prediction table. Only Load instructions that are predicted to be uncorrelated can be executed in disorder. This method avoids a large amount of pipeline flushing while ensuring the correctness of program logic. The test program uses 7 subroutines under SPEC CPU 2006, and the experimental results show that the improved processor's execution performance is improved by 3.5% on average. [ABSTRACT FROM AUTHOR] |
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| Database: |
Engineering Source |
