Analysis of the Impact of the Inductive Peaking Bandwidth Enhancement Technique on the Noise Performance of CMOS Optical Amplifiers.
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| Title: | Analysis of the Impact of the Inductive Peaking Bandwidth Enhancement Technique on the Noise Performance of CMOS Optical Amplifiers. |
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| Authors: | Jalil, Bahram1 (AUTHOR), Kazemi, Somayeh1,2 (AUTHOR) s.kazemi@pel.iaun.ac.ir, Dolatshahi, Mehdi1 (AUTHOR) |
| Source: | Circuits, Systems & Signal Processing. Nov2024, Vol. 43 Issue 11, p6733-6755. 23p. |
| Subjects: | CMOS amplifiers, Optical amplifiers, Optical receivers, Power resources, Reference values, Voltage-controlled oscillators |
| Abstract: | In this paper, the impact of the inductive peaking bandwidth enhancement technique on the input-referred noise performance of a 10 Gbps optical receiver, which includes the CMOS Regulated Cascode (RGC) Transimpedance Amplifier (TIA) is investigated and analyzed. By examining the noise equations in this paper, a novel low-noise design methodology, is introduced. Additionally, through the implementation of the structured g m / I D approach and by selecting the suitable transistor dimensions, the power consumption as well as the noise values are reduced, while the values of the obtained gain and bandwidth are increased. To verify the performance of the designed TIA, the circuit is simulated in HSPICE using 90 nm CMOS technology parameters. The simulation results show the obtained gain value of 55.45 dBΩ, a bandwidth of 7.51 GHz and an input referenced noise value of 15.7 pA/√Hz at the 1.2 V power supply, while the circuit consumes 0.75 mW of power. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | In this paper, the impact of the inductive peaking bandwidth enhancement technique on the input-referred noise performance of a 10 Gbps optical receiver, which includes the CMOS Regulated Cascode (RGC) Transimpedance Amplifier (TIA) is investigated and analyzed. By examining the noise equations in this paper, a novel low-noise design methodology, is introduced. Additionally, through the implementation of the structured g m / I D approach and by selecting the suitable transistor dimensions, the power consumption as well as the noise values are reduced, while the values of the obtained gain and bandwidth are increased. To verify the performance of the designed TIA, the circuit is simulated in HSPICE using 90 nm CMOS technology parameters. The simulation results show the obtained gain value of 55.45 dBΩ, a bandwidth of 7.51 GHz and an input referenced noise value of 15.7 pA/√Hz at the 1.2 V power supply, while the circuit consumes 0.75 mW of power. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 0278081X |
| DOI: | 10.1007/s00034-024-02744-9 |
