In-field Built-in Self-Test for Detecting Incipient Faults in Analog Reconfigurable Filters.
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| Title: | In-field Built-in Self-Test for Detecting Incipient Faults in Analog Reconfigurable Filters. |
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| Authors: | Vélez Ibarra, María Delfina1 (AUTHOR) delfinavelez@unc.edu.ar, Vodanovic, Gonzalo1,2 (AUTHOR) gvodanovic@unc.edu.ar, Laprovitta, Agustín1,3 (AUTHOR) alaprovitta@unc.edu.ar, Peretti, Gabriela1,2 (AUTHOR) gabriela.peretti@unc.edu.ar, Romero, Eduardo1,2 (AUTHOR) eromero@frvm.utn.edu.ar |
| Source: | Circuits, Systems & Signal Processing. Feb2025, Vol. 44 Issue 2, p715-748. 34p. |
| Subjects: | Signal generators, Artificial intelligence, Signal processing, Integrated circuits, Transient analysis |
| Abstract: | In critical applications, a fault in the analog sections of a complex integrated circuit implies severe risks, compromising the mission or potentially causing harm to the people or the ambient. In this context, detecting faults during the operation in the field becomes mandatory, and built-in self-test (BIST) arises as suitable for this purpose. This paper presents an innovative user-oriented in-field BIST solution for switched-capacitor (SC) filters embedded in analog-configurable PSoC™ analog coprocessor (PSoC-AC) from Infineon Technologies AG. The BIST targets catastrophic faults in switches and deviation faults in capacitors, adopting the single-fault paradigm. The method is based on comparing the time-domain responses of the filter (for step input) against a pre-established pattern using a low computational cost signal similarity measure (SSM). The scheme implements the test signal generator and response analyzer with the resources available in the selected platform. This, along with the simple SSM used, achieves zero hardware overhead and low penalty in the memory available for the user application. The method does not require sophisticated signal processing techniques, reducing it to a simple offset removal process. The paper reports an extensive experimental fault injection and measurements campaign. Additionally, it extends the evaluations through fault simulation characterization using a low-cost filter model to establish the lowest deviation fault the method can detect in capacitors. The results show an outstanding performance, detecting all the considered catastrophic faults. Regarding deviation faults, the method detects incipient ones, which is a relevant aspect because the BIST can detect degradations at an early stage. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | In critical applications, a fault in the analog sections of a complex integrated circuit implies severe risks, compromising the mission or potentially causing harm to the people or the ambient. In this context, detecting faults during the operation in the field becomes mandatory, and built-in self-test (BIST) arises as suitable for this purpose. This paper presents an innovative user-oriented in-field BIST solution for switched-capacitor (SC) filters embedded in analog-configurable PSoC™ analog coprocessor (PSoC-AC) from Infineon Technologies AG. The BIST targets catastrophic faults in switches and deviation faults in capacitors, adopting the single-fault paradigm. The method is based on comparing the time-domain responses of the filter (for step input) against a pre-established pattern using a low computational cost signal similarity measure (SSM). The scheme implements the test signal generator and response analyzer with the resources available in the selected platform. This, along with the simple SSM used, achieves zero hardware overhead and low penalty in the memory available for the user application. The method does not require sophisticated signal processing techniques, reducing it to a simple offset removal process. The paper reports an extensive experimental fault injection and measurements campaign. Additionally, it extends the evaluations through fault simulation characterization using a low-cost filter model to establish the lowest deviation fault the method can detect in capacitors. The results show an outstanding performance, detecting all the considered catastrophic faults. Regarding deviation faults, the method detects incipient ones, which is a relevant aspect because the BIST can detect degradations at an early stage. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 0278081X |
| DOI: | 10.1007/s00034-024-02819-7 |