Demonstration of Integrated Quasi-Vertical DMOS Compatible with the Bipolar-CMOS-DMOS Process Achieving Ultralow R ON,sp.
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| Title: | Demonstration of Integrated Quasi-Vertical DMOS Compatible with the Bipolar-CMOS-DMOS Process Achieving Ultralow R ON,sp. |
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| Authors: | Lin, Feng1,2 (AUTHOR) 230219353@seu.edu.cn, Wu, Tuanzhuang1 (AUTHOR) 230228400@seu.edu.cn, Wang, Weidong1 (AUTHOR) 220226200@seu.edu.cn, Wang, Zhengxuan1 (AUTHOR) 220236426@seu.edu.cn, Zhang, Yi2 (AUTHOR), Li, Sheng1 (AUTHOR) seulisheng@seu.edu.cn, Ye, Ran1 (AUTHOR) 101300309@seu.edu.cn, Zhang, Long1 (AUTHOR) longzhang@seu.edu.cn, Wei, Jiaxing1 (AUTHOR) jiaxingwei@seu.edu.cn, Liu, Siyang1 (AUTHOR), Sun, Weifeng1 (AUTHOR) jiaxingwei@seu.edu.cn |
| Source: | Nanomaterials (2079-4991). Feb2025, Vol. 15 Issue 3, p172. 9p. |
| Subjects: | Electric field effects, Metal oxide semiconductor field-effect transistors, Trenches, Voltage |
| Abstract: | An integrated quasi-vertical double-diffused MOSFET (DMOS) with split-gate trench (SGT) structure (SGT-QVDMOS), whose specific ON-state resistance (RON,sp) breaks the traditional Si limit significantly, is proposed and fabricated. The measured data of the latest manufactured device is presented. By introducing the vertical gate poly, the split grounded source poly, and the asymmetric thick oxide in the gate trench, the traditional lateral drift region is folded in the SGT-QVDMOS. In this way, the device voltage withstanding mode transforms from one dimension to two dimensions, including the horizontal and the vertical directions. Combining the electric field modulation effect and the reduced lateral area, which benefit from the quasi-vertical structure, the forward conducting characteristic of the SGT-QVDMOS is effectively improved. According to the measured results from the SGT-QVDMOS manufactured by the 180 nm Bipolar-CMOS-DMOS (BCD) process, the ultralow ON-state resistance is obtained. The device achieves 1.9 V VTH, 11.07 mΩ∙mm2 RON,sp, and 48.6 V BV, which is 39.0% lower than the traditional Si limit. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | An integrated quasi-vertical double-diffused MOSFET (DMOS) with split-gate trench (SGT) structure (SGT-QVDMOS), whose specific ON-state resistance (RON,sp) breaks the traditional Si limit significantly, is proposed and fabricated. The measured data of the latest manufactured device is presented. By introducing the vertical gate poly, the split grounded source poly, and the asymmetric thick oxide in the gate trench, the traditional lateral drift region is folded in the SGT-QVDMOS. In this way, the device voltage withstanding mode transforms from one dimension to two dimensions, including the horizontal and the vertical directions. Combining the electric field modulation effect and the reduced lateral area, which benefit from the quasi-vertical structure, the forward conducting characteristic of the SGT-QVDMOS is effectively improved. According to the measured results from the SGT-QVDMOS manufactured by the 180 nm Bipolar-CMOS-DMOS (BCD) process, the ultralow ON-state resistance is obtained. The device achieves 1.9 V VTH, 11.07 mΩ∙mm2 RON,sp, and 48.6 V BV, which is 39.0% lower than the traditional Si limit. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 20794991 |
| DOI: | 10.3390/nano15030172 |
