Reduction of Interference Terms in Wigner Ville Distribution using Machine Learning.
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| Title: | Reduction of Interference Terms in Wigner Ville Distribution using Machine Learning. |
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| Authors: | Satyanarayana, S. V. V.1 (AUTHOR) svvsatyanarayana8589@gmail.com, Murali Krishna, B.1 (AUTHOR) murali.ece713@gmail.com, Satyanarayana, P. V. V.1 (AUTHOR) pvv.bunni@gmail.com, Kusuma Kumari, E.1 (AUTHOR) kusuma.madhu.ece@gmail.com |
| Source: | Circuits, Systems & Signal Processing. Mar2025, Vol. 44 Issue 3, p2041-2072. 32p. |
| Subjects: | Verilog (Computer hardware description language), Field programmable gate arrays, Wigner distribution, Power density, Machine learning |
| Abstract: | The present work introduces an Field Programmable Gate Array (FPGA) implementation of the Fractional Fourier filtering technique (FrFt) to reduce the issue of interference-terms in the Wigner-Ville Distribution (WVD). The WVD offers an effective view of a signal's time-frequency representation (TFR) in terms of power density components. However, WVD computation results in both auto terms (ATs) and cross-terms (CTs) due to product operation between the signal and its conjugate symmetric signal. To address this, the FrFt is used to rotate the input signal in the TFR plane to detect the presence of CTs. Once CTs are detected in the TFR plane, the Sobel filter is used to identify the edge features of ATs and CTs. The identified edge features are then fed to the proposed K-means++ algorithm to form the clusters. The proposed K-means++ employs the centroid for each group by adapting Brent's method. The formed clustered groups are processed through designed band-pass and stop-band filters to eliminate the detected CTs. Subsequently, the WVD is applied to the obtained individual auto terms of the signal, yielding an interference term-free TFR. The proposed methodology is implemented on Zinc-7000 Series (FPGA family) using Verilog hardware description language (HDL), and the design flow is detailed. To validate the effectiveness of the proposed method, chirp signals and Electrocardiogram signals are taken as input for testing purposes. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | The present work introduces an Field Programmable Gate Array (FPGA) implementation of the Fractional Fourier filtering technique (FrFt) to reduce the issue of interference-terms in the Wigner-Ville Distribution (WVD). The WVD offers an effective view of a signal's time-frequency representation (TFR) in terms of power density components. However, WVD computation results in both auto terms (ATs) and cross-terms (CTs) due to product operation between the signal and its conjugate symmetric signal. To address this, the FrFt is used to rotate the input signal in the TFR plane to detect the presence of CTs. Once CTs are detected in the TFR plane, the Sobel filter is used to identify the edge features of ATs and CTs. The identified edge features are then fed to the proposed K-means++ algorithm to form the clusters. The proposed K-means++ employs the centroid for each group by adapting Brent's method. The formed clustered groups are processed through designed band-pass and stop-band filters to eliminate the detected CTs. Subsequently, the WVD is applied to the obtained individual auto terms of the signal, yielding an interference term-free TFR. The proposed methodology is implemented on Zinc-7000 Series (FPGA family) using Verilog hardware description language (HDL), and the design flow is detailed. To validate the effectiveness of the proposed method, chirp signals and Electrocardiogram signals are taken as input for testing purposes. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 0278081X |
| DOI: | 10.1007/s00034-024-02916-7 |