View in EDS

Fast and ultra-low energy subthreshold level shifter using split-gate buffer for low-power digital VLSI systems.

Saved in:
Bibliographic Details
Title: Fast and ultra-low energy subthreshold level shifter using split-gate buffer for low-power digital VLSI systems.
Authors: Sivakumar, S. A.1 (AUTHOR) drsivakumar.sa@gmail.com, Senthilkumar, B.2 (AUTHOR) senthilkit2016@gmail.com, Rajendran, Selvakumar3 (AUTHOR) selvaonto@gmail.com
Source: Analog Integrated Circuits & Signal Processing. May2025, Vol. 123 Issue 2, p1-11. 11p.
Abstract: Low-energy operation is predominant feature in the modern wireless sensor node and implantable biomedical applications. Scaling the supply voltage towards sub-/near-threshold level is vital design methodology to achieve energy-efficient operation. Voltage scaling can be adopted in the multiple supply voltage design incorporating interfacing circuit called voltage level shifters to attain power-efficient operation. This paper presents differential cascode voltage switch structure based high-speed and low-energy voltage level shifter for converting subthreshold voltage to nominal output voltage. The proposed level shifter (LS) utilizes NMOS/PMOS diode pairs along with the cross-coupled PMOS to address the current contention issue by suppressing the current from pull-up network while pull-down network is activated. The switching speed of the level conversion is enhanced by pass transistor and boosting devices in the pull-down network. Further, split-gate inverter/buffer at the output stage ensures high performance by alleviating static power and accelerating speed performance. The proposed LS is implemented in CMOS 180 nm technology on Cadence (Virtuoso) platform and analyzed using Spectre circuit simulator. The simulation results reveal the subthreshold level conversion from 220 mV to 1.8 V and wider frequency range of conversion. In addition, it ensures the delay of 8.57 ns, energy/transition of 39.4 fJ for level conversion from 0.4 to 1.8 V with input signal frequency of 1 MHz. Moreover, the LS consumes static power of 0.302 nW at standby mode. [ABSTRACT FROM AUTHOR]
Copyright of Analog Integrated Circuits & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
Description
Abstract:Low-energy operation is predominant feature in the modern wireless sensor node and implantable biomedical applications. Scaling the supply voltage towards sub-/near-threshold level is vital design methodology to achieve energy-efficient operation. Voltage scaling can be adopted in the multiple supply voltage design incorporating interfacing circuit called voltage level shifters to attain power-efficient operation. This paper presents differential cascode voltage switch structure based high-speed and low-energy voltage level shifter for converting subthreshold voltage to nominal output voltage. The proposed level shifter (LS) utilizes NMOS/PMOS diode pairs along with the cross-coupled PMOS to address the current contention issue by suppressing the current from pull-up network while pull-down network is activated. The switching speed of the level conversion is enhanced by pass transistor and boosting devices in the pull-down network. Further, split-gate inverter/buffer at the output stage ensures high performance by alleviating static power and accelerating speed performance. The proposed LS is implemented in CMOS 180 nm technology on Cadence (Virtuoso) platform and analyzed using Spectre circuit simulator. The simulation results reveal the subthreshold level conversion from 220 mV to 1.8 V and wider frequency range of conversion. In addition, it ensures the delay of 8.57 ns, energy/transition of 39.4 fJ for level conversion from 0.4 to 1.8 V with input signal frequency of 1 MHz. Moreover, the LS consumes static power of 0.302 nW at standby mode. [ABSTRACT FROM AUTHOR]
ISSN:09251030
DOI:10.1007/s10470-025-02377-1