Single Miller Compensation Based Four Stage CMOS Amplifier.
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| Title: | Single Miller Compensation Based Four Stage CMOS Amplifier. |
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| Authors: | Moafi, Ali1 (AUTHOR) Ali.Moafi2024@gmail.com, Dehbovid, Hadi1 (AUTHOR) Hadi.Dehbovid@iau.ac.ir, Adarang, Habib2 (AUTHOR) HabibAdarang@gmail.com, Ghoreishi Amiri, Seyed Saleh1 (AUTHOR) SalehGhoreyshi@gmail.com |
| Source: | IETE Journal of Research. Mar2025, Vol. 71 Issue 3, p1040-1049. 10p. |
| Subjects: | CMOS amplifiers, Transfer functions, Sensitivity analysis, Capacitors |
| Abstract: | Like reversed nested Miller compensation, four nested Miller loops are exploited as a compensation network for a four-stage amplifier. However, isolating the feed-forward path via two differential stages allows the use of a single Miller compensation capacitor while the output node remains intact regarding capacitive loading from compensation. The exploited configuration for the compensation network provides the capability of reducing the number and size of needed capacitors due to positioning at the outputs of differential stages. This scenario is linearly modeled by a transfer function, then a circuit realization is suggested and simulated using 0.18 µm CMOS technology. According to the simulation results, the proposed amplifier can obtain 158 dB DC gain, 11.2 MHz GBW, and 84° PM while consuming 298 µW. Ample sensitivity analysis verifies the robustness of the proposed amplifier against probable mismatches and errors. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | Like reversed nested Miller compensation, four nested Miller loops are exploited as a compensation network for a four-stage amplifier. However, isolating the feed-forward path via two differential stages allows the use of a single Miller compensation capacitor while the output node remains intact regarding capacitive loading from compensation. The exploited configuration for the compensation network provides the capability of reducing the number and size of needed capacitors due to positioning at the outputs of differential stages. This scenario is linearly modeled by a transfer function, then a circuit realization is suggested and simulated using 0.18 µm CMOS technology. According to the simulation results, the proposed amplifier can obtain 158 dB DC gain, 11.2 MHz GBW, and 84° PM while consuming 298 µW. Ample sensitivity analysis verifies the robustness of the proposed amplifier against probable mismatches and errors. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 03772063 |
| DOI: | 10.1080/03772063.2024.2434588 |
