Design and Characterization of a 3.5 GHz CMOS Power Amplifier for Low-Band 5G Applications.
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| Title: | Design and Characterization of a 3.5 GHz CMOS Power Amplifier for Low-Band 5G Applications. |
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| Authors: | Hasan, Ahmad Fariz1,2 (AUTHOR) farizhasan@unimap.edu.my, Zainol Murad, Sohiful Anuar1,2 (AUTHOR) sohiful@unimap.edu.my, Abu Bakar, Faizah1,2 (AUTHOR) faizahbakar@unimap.edu.my, Sapawi, Rohana3 (AUTHOR) srohana@unimas.edu.my |
| Source: | IETE Journal of Research. Mar2025, Vol. 71 Issue 3, p1009-1015. 7p. |
| Subjects: | CMOS amplifiers, Complementary metal oxide semiconductors, Radio frequency, 5G networks, Transistors |
| Abstract: | A 3.5 GHz CMOS power amplifier (PA) designed for 5G applications is presented in this study, utilizing the 0.18 µm RF CMOS process technology. The circuit architecture comprises two stages: the first stage employs a cascode topology with a negative voltage applied to the transistor body technique to achieve sufficient gain and minimize current, thereby reducing power consumption. In the second stage, to ensure high efficiency, a class-E amplifier is being used. Measurement results indicate a power gain (S21) of 17.2 dB, a power-added efficiency (PAE) of 45.6% and a saturated power (Psat) of 8.5 dBm, obtained at 3.5 GHz. These findings validate the suitability of the proposed design at low-band frequency for 5G applications. The chip area for the proposed design is 2.45 mm². The discrepancy between simulation and measurement is due to the parasitic in the layout design. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | A 3.5 GHz CMOS power amplifier (PA) designed for 5G applications is presented in this study, utilizing the 0.18 µm RF CMOS process technology. The circuit architecture comprises two stages: the first stage employs a cascode topology with a negative voltage applied to the transistor body technique to achieve sufficient gain and minimize current, thereby reducing power consumption. In the second stage, to ensure high efficiency, a class-E amplifier is being used. Measurement results indicate a power gain (S21) of 17.2 dB, a power-added efficiency (PAE) of 45.6% and a saturated power (Psat) of 8.5 dBm, obtained at 3.5 GHz. These findings validate the suitability of the proposed design at low-band frequency for 5G applications. The chip area for the proposed design is 2.45 mm². The discrepancy between simulation and measurement is due to the parasitic in the layout design. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 03772063 |
| DOI: | 10.1080/03772063.2024.2439033 |
