An Efficient Frequency Compensation Approach for Multi‐Stage CMOS Amplifiers.
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| Title: | An Efficient Frequency Compensation Approach for Multi‐Stage CMOS Amplifiers. |
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| Authors: | Khadem, Mohammad Saeed1 (AUTHOR), Rezaei Borjlu, Shaban1 (AUTHOR) shaban.rezaei@iau.ac.ir, Makkiabadi, Bahador2 (AUTHOR) |
| Source: | International Journal of Numerical Modelling. May/Jun2025, Vol. 38 Issue 3, p1-16. 16p. |
| Subjects: | CMOS amplifiers, Data conversion, Transfer functions, Capacitors, Detectors |
| Abstract: | Leveraging Miller's concept, a general approach for multi‐stage amplifier frequency compensation is proposed. The idea is repeating a Miller pattern on intermediate nodes. In this way Miller capacitor at the output of a differential gain stage, manipulates poles and zeros locations to achieve the desired frequency response. The idea is applied to four and five‐stage amplifiers. The linear transfer function (TF) and poles‐zeros formulations are calculated for both amplifiers while circuit implementations are simulated using 0.18 μm CMOS technology. According to both theoretical description and simulation results, the proposed frequency compensation appropriately stabilized the amplifier with excellent performance. Obtaining more than 13 MHz for GBW with 83° phase margin while whole the four‐stage amplifier consumes less than 320 μW. Ample simulation results are provided to express the reliability and robustness of the proposed approach. In this view, the proposed compensation method besides its design methodology can be used for almost any analog and mix‐mode systems such as modulators, sensors, and data converters. [ABSTRACT FROM AUTHOR] |
| Copyright of International Journal of Numerical Modelling is the property of Wiley-Blackwell and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Abstract: | Leveraging Miller's concept, a general approach for multi‐stage amplifier frequency compensation is proposed. The idea is repeating a Miller pattern on intermediate nodes. In this way Miller capacitor at the output of a differential gain stage, manipulates poles and zeros locations to achieve the desired frequency response. The idea is applied to four and five‐stage amplifiers. The linear transfer function (TF) and poles‐zeros formulations are calculated for both amplifiers while circuit implementations are simulated using 0.18 μm CMOS technology. According to both theoretical description and simulation results, the proposed frequency compensation appropriately stabilized the amplifier with excellent performance. Obtaining more than 13 MHz for GBW with 83° phase margin while whole the four‐stage amplifier consumes less than 320 μW. Ample simulation results are provided to express the reliability and robustness of the proposed approach. In this view, the proposed compensation method besides its design methodology can be used for almost any analog and mix‐mode systems such as modulators, sensors, and data converters. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 08943370 |
| DOI: | 10.1002/jnm.70024 |
