ReHuff: 基于ReRAM的Huffman编码硬件结构设计.

Saved in:
Bibliographic Details
Title: ReHuff: 基于ReRAM的Huffman编码硬件结构设计.
Alternate Title: ReHuff:A Huffman coding hardware architecture based on ReRAM.
Authors: 郑道文1, 周一开1, 唐忆滨2,3, 刘博生1, 武继刚1 asjgwucn@outlook.com
Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Jun2025, Vol. 47 Issue 6, p988-997. 10p.
Subjects: Huffman codes, Random access memory, Nonvolatile random-access memory, Data compression, Architectural design, Deep learning
Abstract (English): With the rapid expansion of data volume in various application scenarios such as deep learning, the hardware overhead of communication and storage has significantly increased. Against this backdrop, the importance of compression methods has grown substantially. Huffman coding is one of the most representative and widely used compression methods, known for effectively compressing data and saving storage space without compro-mising data integrity. However, due to the limitations of hierarchical memory storage, traditional hardware solutions for Huffman coding face challenges of high latency and energy consumption. This paper proposes a hardware architecture named ReHuff, which leverages resistive random-access memory (ReRAM) to enable in-memory Huffman encoding, and designs a ReRAM-based Huffman coding mapping method to extract valid data. To address the mismatch between variable-length encoded data and fixed-length ReRAM blocks during mapping, a dual-stage variable-length data selection and segmentation approach is proposed, adapting to the architectural design to integrate variable-length outputs, thereby reducing energy consumption and improving ReRAM utilization efficiency. Simulation results demonstrate that the proposed design out-performs representative benchmarks, improving performance by 18.6 times and reducing energy consumption by 82.4%. [ABSTRACT FROM AUTHOR]
Abstract (Chinese): 随着数据量在深度学习等各种应用场景中的迅速增大, 通信和存储的硬件开销显著增加。在此背景下, 压缩方法的重要性日益提升。哈夫曼编码是目前具备代表性且广泛应用的压缩方法之一, 其特点是在不损害数据完整性的前提下, 有效压缩数据并节省存储空间。然而, 由于分层内存存储的限制, 哈夫曼编码在传统硬件中的解决方案面临着高延迟和高能耗的挑战。提出了一种名为ReHuff的硬件架构, 利用阻变随机存储器 (ReRAM) 实现在内存中直接进行哈夫曼编码。设计了基于ReRAM的哈夫曼编码映射方法, 以提取有效数据。针对映射过程中存在的变长编码数据与定长ReRAM块之间的匹配问题, 提出了适应架构设计的双阶段变长数据选择与分割方法, 整合变长输出以节省能耗并提升ReRAM的利用效率。仿真结果表明, 所提出的设计方案的性能与能耗表现均优于代表性基准, 在性能方面提高了18.6倍, 在能耗方面降低了82.4%。 [ABSTRACT FROM AUTHOR]
Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
Description
Abstract:With the rapid expansion of data volume in various application scenarios such as deep learning, the hardware overhead of communication and storage has significantly increased. Against this backdrop, the importance of compression methods has grown substantially. Huffman coding is one of the most representative and widely used compression methods, known for effectively compressing data and saving storage space without compro-mising data integrity. However, due to the limitations of hierarchical memory storage, traditional hardware solutions for Huffman coding face challenges of high latency and energy consumption. This paper proposes a hardware architecture named ReHuff, which leverages resistive random-access memory (ReRAM) to enable in-memory Huffman encoding, and designs a ReRAM-based Huffman coding mapping method to extract valid data. To address the mismatch between variable-length encoded data and fixed-length ReRAM blocks during mapping, a dual-stage variable-length data selection and segmentation approach is proposed, adapting to the architectural design to integrate variable-length outputs, thereby reducing energy consumption and improving ReRAM utilization efficiency. Simulation results demonstrate that the proposed design out-performs representative benchmarks, improving performance by 18.6 times and reducing energy consumption by 82.4%. [ABSTRACT FROM AUTHOR]
ISSN:1007130X
DOI:10.3969/j.issn.1007-130X.2025.06.005