Energy-Efficient FinFET SRAM Design for In-Memory Computing Applications.

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Bibliographic Details
Title:	Energy-Efficient FinFET SRAM Design for In-Memory Computing Applications.
Authors:	Garg, Deepak¹ deepakgarg1985@gmail.com, Singh, Rupali² rupalis@srmist.edu.in, Singh, Pankaj³ singhpankaj76@gmail.com
Source:	IAENG International Journal of Computer Science. Sep2025, Vol. 52 Issue 9, p3022-3034. 13p.
Subjects:	Static random access memory, Leakage, Transistors, Power resources management, Cache memory, Energy consumption, Semiconductor technology, Electric power consumption
Abstract:	In today's era, lifespan of batteries drops quickly as the power usage of devices improves. Reducing leakage current (ILeakage) during integrated circuit design is crucial, despite the exponential growth in demand for lowpower devices. FinFET solves this problem by enhancing challenging power versus performance choices. This study recommends using self-controllable voltage-level approaches to create FinFET-based 7-transistor SRAM cells. An SVL circuit can reduce an SRAM cell's standby leakage power. There are two methods, one of which raises the ground potential and the other lowers the supply voltage. The design given gets a minimum power of 24.29 nW and a low leakage current of 9.46 nA by using both USVL and LSVL techniques together. The proposed SRAM cell design saves 10% in power and 31% in leakage compared to SRAM cells made with USVL and LVSL cells, respectively using Cadence Virtuoso software on a 45 nm FinFET process technology. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	In today's era, lifespan of batteries drops quickly as the power usage of devices improves. Reducing leakage current (ILeakage) during integrated circuit design is crucial, despite the exponential growth in demand for lowpower devices. FinFET solves this problem by enhancing challenging power versus performance choices. This study recommends using self-controllable voltage-level approaches to create FinFET-based 7-transistor SRAM cells. An SVL circuit can reduce an SRAM cell's standby leakage power. There are two methods, one of which raises the ground potential and the other lowers the supply voltage. The design given gets a minimum power of 24.29 nW and a low leakage current of 9.46 nA by using both USVL and LSVL techniques together. The proposed SRAM cell design saves 10% in power and 31% in leakage compared to SRAM cells made with USVL and LVSL cells, respectively using Cadence Virtuoso software on a 45 nm FinFET process technology. [ABSTRACT FROM AUTHOR]
ISSN:	1819656X