A look ahead sliding decision feedback equalizer for 112 Gbit/s SerDes receiver.

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Bibliographic Details
Title:	A look ahead sliding decision feedback equalizer for 112 Gbit/s SerDes receiver.
Authors:	YANG, Zhouhao¹ yzh@nudt.edu.cn, LÜ, Fangxu¹ lvfangxu1988@nudt.edu.cn, XU, Weixia¹ xuweixia@nudt.edu.cn, LI, Shijie¹ lishijienudt@163.com, XU, Chaolong¹, HU, Xiaoyue¹
Source:	Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Jul2025, Vol. 47 Issue 7, p1162-1169. 8p.
Subjects:	Decision feedback equalizers, Forward error correction, Digital signal processing, Bit error rate, Information technology
Abstract:	With the continuous advancement of information technology, wireline data rates have experienced a significant leap from 112 Gbit/s to 224 Gbit/s. The increase in data rates has raised the complexity requirements for SerDes receiver equalizers. To address timing constraints and other issues brought about by complex equalizer structures, a sliding block decision feedback equalizer based on a look ahead structure is proposed. The design incorporates a 6-tap feed-forward equalizer (FFE) and a 9-tap decision feedback equalizer (DFE) for digital signal processing. Functional validation is conducted through MATLAB simulation modeling. The results show that at a data rate of 112 Gbit/s, under channel attenuation ranging from 8 dB to 35 dB, this digital signal processing design, which utilizes a least mean squares (LMS) adaptive equalization algorithm, can effectively reduce the bit error rate (BER). The BER performance meets the discrimination requirements of KP4 forward error correction (FEC) and demonstrates superior performance compared to traditional equalizer structures. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

Description
Abstract:	With the continuous advancement of information technology, wireline data rates have experienced a significant leap from 112 Gbit/s to 224 Gbit/s. The increase in data rates has raised the complexity requirements for SerDes receiver equalizers. To address timing constraints and other issues brought about by complex equalizer structures, a sliding block decision feedback equalizer based on a look ahead structure is proposed. The design incorporates a 6-tap feed-forward equalizer (FFE) and a 9-tap decision feedback equalizer (DFE) for digital signal processing. Functional validation is conducted through MATLAB simulation modeling. The results show that at a data rate of 112 Gbit/s, under channel attenuation ranging from 8 dB to 35 dB, this digital signal processing design, which utilizes a least mean squares (LMS) adaptive equalization algorithm, can effectively reduce the bit error rate (BER). The BER performance meets the discrimination requirements of KP4 forward error correction (FEC) and demonstrates superior performance compared to traditional equalizer structures. [ABSTRACT FROM AUTHOR]
ISSN:	1007130X
DOI:	10.3969/j.issn.1007-130X.2025.07.003