A look ahead sliding decision feedback equalizer for 112 Gbit/s SerDes receiver.
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| Title: | A look ahead sliding decision feedback equalizer for 112 Gbit/s SerDes receiver. |
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| Authors: | YANG, Zhouhao1 yzh@nudt.edu.cn, LÜ, Fangxu1 lvfangxu1988@nudt.edu.cn, XU, Weixia1 xuweixia@nudt.edu.cn, LI, Shijie1 lishijienudt@163.com, XU, Chaolong1, HU, Xiaoyue1 |
| Source: | Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Jul2025, Vol. 47 Issue 7, p1162-1169. 8p. |
| Subjects: | Decision feedback equalizers, Forward error correction, Digital signal processing, Bit error rate, Information technology |
| Abstract: | With the continuous advancement of information technology, wireline data rates have experienced a significant leap from 112 Gbit/s to 224 Gbit/s. The increase in data rates has raised the complexity requirements for SerDes receiver equalizers. To address timing constraints and other issues brought about by complex equalizer structures, a sliding block decision feedback equalizer based on a look ahead structure is proposed. The design incorporates a 6-tap feed-forward equalizer (FFE) and a 9-tap decision feedback equalizer (DFE) for digital signal processing. Functional validation is conducted through MATLAB simulation modeling. The results show that at a data rate of 112 Gbit/s, under channel attenuation ranging from 8 dB to 35 dB, this digital signal processing design, which utilizes a least mean squares (LMS) adaptive equalization algorithm, can effectively reduce the bit error rate (BER). The BER performance meets the discrimination requirements of KP4 forward error correction (FEC) and demonstrates superior performance compared to traditional equalizer structures. [ABSTRACT FROM AUTHOR] |
| Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
| FullText | Links: – Type: pdflink Text: Availability: 0 |
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| Header | DbId: egs DbLabel: Engineering Source An: 187879541 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: A look ahead sliding decision feedback equalizer for 112 Gbit/s SerDes receiver. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22YANG%2C+Zhouhao%22">YANG, Zhouhao</searchLink><relatesTo>1</relatesTo><i> yzh@nudt.edu.cn</i><br /><searchLink fieldCode="AR" term="%22LÜ%2C+Fangxu%22">LÜ, Fangxu</searchLink><relatesTo>1</relatesTo><i> lvfangxu1988@nudt.edu.cn</i><br /><searchLink fieldCode="AR" term="%22XU%2C+Weixia%22">XU, Weixia</searchLink><relatesTo>1</relatesTo><i> xuweixia@nudt.edu.cn</i><br /><searchLink fieldCode="AR" term="%22LI%2C+Shijie%22">LI, Shijie</searchLink><relatesTo>1</relatesTo><i> lishijienudt@163.com</i><br /><searchLink fieldCode="AR" term="%22XU%2C+Chaolong%22">XU, Chaolong</searchLink><relatesTo>1</relatesTo><br /><searchLink fieldCode="AR" term="%22HU%2C+Xiaoyue%22">HU, Xiaoyue</searchLink><relatesTo>1</relatesTo> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Computer+Engineering+%26+Science+%2F+Jisuanji+Gongcheng+yu+Kexue%22">Computer Engineering & Science / Jisuanji Gongcheng yu Kexue</searchLink>. Jul2025, Vol. 47 Issue 7, p1162-1169. 8p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Decision+feedback+equalizers%22">Decision feedback equalizers</searchLink><br /><searchLink fieldCode="DE" term="%22Forward+error+correction%22">Forward error correction</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+signal+processing%22">Digital signal processing</searchLink><br /><searchLink fieldCode="DE" term="%22Bit+error+rate%22">Bit error rate</searchLink><br /><searchLink fieldCode="DE" term="%22Information+technology%22">Information technology</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: With the continuous advancement of information technology, wireline data rates have experienced a significant leap from 112 Gbit/s to 224 Gbit/s. The increase in data rates has raised the complexity requirements for SerDes receiver equalizers. To address timing constraints and other issues brought about by complex equalizer structures, a sliding block decision feedback equalizer based on a look ahead structure is proposed. The design incorporates a 6-tap feed-forward equalizer (FFE) and a 9-tap decision feedback equalizer (DFE) for digital signal processing. Functional validation is conducted through MATLAB simulation modeling. The results show that at a data rate of 112 Gbit/s, under channel attenuation ranging from 8 dB to 35 dB, this digital signal processing design, which utilizes a least mean squares (LMS) adaptive equalization algorithm, can effectively reduce the bit error rate (BER). The BER performance meets the discrimination requirements of KP4 forward error correction (FEC) and demonstrates superior performance compared to traditional equalizer structures. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Computer Engineering & Science / Jisuanji Gongcheng yu Kexue is the property of Computer Engineering & Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.3969/j.issn.1007-130X.2025.07.003 Languages: – Code: chi Text: Chinese PhysicalDescription: Pagination: PageCount: 8 StartPage: 1162 Subjects: – SubjectFull: Decision feedback equalizers Type: general – SubjectFull: Forward error correction Type: general – SubjectFull: Digital signal processing Type: general – SubjectFull: Bit error rate Type: general – SubjectFull: Information technology Type: general Titles: – TitleFull: A look ahead sliding decision feedback equalizer for 112 Gbit/s SerDes receiver. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: YANG, Zhouhao – PersonEntity: Name: NameFull: LÜ, Fangxu – PersonEntity: Name: NameFull: XU, Weixia – PersonEntity: Name: NameFull: LI, Shijie – PersonEntity: Name: NameFull: XU, Chaolong – PersonEntity: Name: NameFull: HU, Xiaoyue IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 07 Text: Jul2025 Type: published Y: 2025 Identifiers: – Type: issn-print Value: 1007130X Numbering: – Type: volume Value: 47 – Type: issue Value: 7 Titles: – TitleFull: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue Type: main |
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