Hardware-friendly rate estimation algorithm and architecture design for AVS3.
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| Title: | Hardware-friendly rate estimation algorithm and architecture design for AVS3. |
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| Authors: | Yan, Yunyao1 (AUTHOR) yunyaoyan@pku.edu.cn, Xiang, Guoqing2 (AUTHOR) gqxiang@pku.edu.cn, Chen, Jie1 (AUTHOR) chenj@pcl.ac.cn, Huang, Xiaofeng3 (AUTHOR) xfhuang@hdu.edu.cn, Zhang, Peng4 (AUTHOR) pzhang@aiit.org.cn, Jia, Huizhu2 (AUTHOR) hzjia@pku.edu.cn, Xie, Xiaodong2 (AUTHOR) dongxie@pku.edu.cn |
| Source: | Multimedia Tools & Applications. Sep2025, Vol. 84 Issue 31, p38777-38795. 19p. |
| Subjects: | Video coding, Video compression standards, Real-time computing, Entropy (Information theory), Computer architecture, Bit rate, Algorithms |
| Abstract: | To enhance the capabilities of advanced video coding for emerging applications, the AVS3 standard has been introduced to double the coding efficiency compared to its predecessor, the AVS2 standard. It incorporates sophisticated coding tools, such as advanced rate-distortion optimization (RDO), to select the optimal coding mode. The AVS3 standard further refines bit rate compression through Advanced Entropy Coding (AEC) within the RDO process. However, AEC demands significant computational resources due to its high data dependency and involves complex steps like binarization, context modeling, interval subdivision, renormalization, handling of outstanding bits, and context updating. Notably, the time complexity of AEC is predominantly due to context updating and interval subdivision, which are recursive and thus pose challenges for real-time applications, particularly in hardware implementations. Addressing these challenges, this paper introduces an adaptive rate estimation algorithm using a hardware-friendly piece-wise linear function to expedite bit rate calculations for AVS3 applications. Initially, we develop a linear rate estimation method based on the statistics of bin numbers. To preserve high coding performance, we further propose an adaptive model parameter updating method that adjusts weights dynamically based on varying video content. Building on this fast rate estimation algorithm, we propose a high-throughput hardware architecture that incorporates pipelining and parallelization to meet the stringent real-time requirements for 4K@120fps ultra-high-definition video at 200 MHz, with only a minimal increase in BD-rate by 1.06% under the All-Intra (AI) configuration. To our knowledge, this is the pioneering study focusing on hardware-oriented rate estimation for the AVS3 standard, marking a significant advancement in the field of video coding technology. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | To enhance the capabilities of advanced video coding for emerging applications, the AVS3 standard has been introduced to double the coding efficiency compared to its predecessor, the AVS2 standard. It incorporates sophisticated coding tools, such as advanced rate-distortion optimization (RDO), to select the optimal coding mode. The AVS3 standard further refines bit rate compression through Advanced Entropy Coding (AEC) within the RDO process. However, AEC demands significant computational resources due to its high data dependency and involves complex steps like binarization, context modeling, interval subdivision, renormalization, handling of outstanding bits, and context updating. Notably, the time complexity of AEC is predominantly due to context updating and interval subdivision, which are recursive and thus pose challenges for real-time applications, particularly in hardware implementations. Addressing these challenges, this paper introduces an adaptive rate estimation algorithm using a hardware-friendly piece-wise linear function to expedite bit rate calculations for AVS3 applications. Initially, we develop a linear rate estimation method based on the statistics of bin numbers. To preserve high coding performance, we further propose an adaptive model parameter updating method that adjusts weights dynamically based on varying video content. Building on this fast rate estimation algorithm, we propose a high-throughput hardware architecture that incorporates pipelining and parallelization to meet the stringent real-time requirements for 4K@120fps ultra-high-definition video at 200 MHz, with only a minimal increase in BD-rate by 1.06% under the All-Intra (AI) configuration. To our knowledge, this is the pioneering study focusing on hardware-oriented rate estimation for the AVS3 standard, marking a significant advancement in the field of video coding technology. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 13807501 |
| DOI: | 10.1007/s11042-025-20727-z |
