Generic 5G NR LDPC Encoder Architecture Optimized for Area and Throughput.
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| Title: | Generic 5G NR LDPC Encoder Architecture Optimized for Area and Throughput. |
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| Authors: | Tarek, Muhammed1 (AUTHOR), Mohamed, Eman2 (AUTHOR), ElSayed, Shaimaa2 (AUTHOR), Elashkar, Nahla3 (AUTHOR) nahlaelazab@eri.sci.eg, Tripathi, Suman Lata (AUTHOR) |
| Source: | Journal of Electrical & Computer Engineering. 9/30/2025, Vol. 2025, p1-18. 18p. |
| Subjects: | 5G networks, Channel coding, Mathematics, Application-specific integrated circuits, Encoding, Software architecture, Mechanical efficiency |
| Abstract: | Physical Downlink Shared Channel (PDSCH) in 5G New Radio (NR) uses LDPC codes as the channel coding solution for their efficient error‐correcting performance and suitability for high‐speed communications. To meet the high‐throughput requirements of the 5G NR technology, this paper discusses different 5G NR LDPC encoder architectures that enable different parallel encoding schemes and optimizes the design for specific metrics. The recent architectural designs might lack effective design metrics that ensure high throughput, low area and gate counts, and full compatibility with the 5G NR standard. The suggested architecture aims to a generic design with flexible controller that is fully compatible with all the supported code block sizes and code rates in the 5G NR standard. The design is implemented in ASIC using NanGate‐15 nm standard cells CMOS technology with The Cadence Genus synthesis solution. The proposed architecture targets high‐throughput encoding operations with a low‐area hardware design. The synthesis of the suggested encoder resulted in a maximum frequency of 1.71 GHz and gate counts of 491.8 K gates with all the code block sizes and code rates in 5G NR standard supported. For the largest code length, the proposed architecture's throughput is up to 451.44 Gbps. Among the discussed previous works, there is one that targets a very high throughput of 257.9 Gbps but implemented using very high gate counts of 1126 K gates for only one code‐word size (25344, 8448). This previous work implements encoding operation in a sub‐matrix‐by‐sub‐matrix encoding scheme. To balance between gate counts and throughput, another previous encoder architecture work, designed for only one code‐word size (23232, 7744), achieved a relatively high throughput of 202.4 Gbps and gate counts of 486.4 K gates. This architecture conducts parallel encoding operation in a row‐by‐row scheme. The results confirmed that the proposed architecture achieves suitable balance between high throughput, gate counts, and 5G NR compatibility compared to the previous works. The postsynthesis results showed a throughput improvement of 123% and 75.04% compared to row‐by‐row and submatrix‐based schemes, respectively. They also show a gate count reduction of 56% and 23.1% compared to submatrix‐based and column‐based schemes, respectively. [ABSTRACT FROM AUTHOR] |
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| Database: | Engineering Source |
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| Abstract: | Physical Downlink Shared Channel (PDSCH) in 5G New Radio (NR) uses LDPC codes as the channel coding solution for their efficient error‐correcting performance and suitability for high‐speed communications. To meet the high‐throughput requirements of the 5G NR technology, this paper discusses different 5G NR LDPC encoder architectures that enable different parallel encoding schemes and optimizes the design for specific metrics. The recent architectural designs might lack effective design metrics that ensure high throughput, low area and gate counts, and full compatibility with the 5G NR standard. The suggested architecture aims to a generic design with flexible controller that is fully compatible with all the supported code block sizes and code rates in the 5G NR standard. The design is implemented in ASIC using NanGate‐15 nm standard cells CMOS technology with The Cadence Genus synthesis solution. The proposed architecture targets high‐throughput encoding operations with a low‐area hardware design. The synthesis of the suggested encoder resulted in a maximum frequency of 1.71 GHz and gate counts of 491.8 K gates with all the code block sizes and code rates in 5G NR standard supported. For the largest code length, the proposed architecture's throughput is up to 451.44 Gbps. Among the discussed previous works, there is one that targets a very high throughput of 257.9 Gbps but implemented using very high gate counts of 1126 K gates for only one code‐word size (25344, 8448). This previous work implements encoding operation in a sub‐matrix‐by‐sub‐matrix encoding scheme. To balance between gate counts and throughput, another previous encoder architecture work, designed for only one code‐word size (23232, 7744), achieved a relatively high throughput of 202.4 Gbps and gate counts of 486.4 K gates. This architecture conducts parallel encoding operation in a row‐by‐row scheme. The results confirmed that the proposed architecture achieves suitable balance between high throughput, gate counts, and 5G NR compatibility compared to the previous works. The postsynthesis results showed a throughput improvement of 123% and 75.04% compared to row‐by‐row and submatrix‐based schemes, respectively. They also show a gate count reduction of 56% and 23.1% compared to submatrix‐based and column‐based schemes, respectively. [ABSTRACT FROM AUTHOR] |
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| ISSN: | 20900147 |
| DOI: | 10.1155/jece/1104969 |
