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A 0.05–20 GHz ultra-wideband CMOS circulator with differential compensation transistors and differential delay lines.

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Title: A 0.05–20 GHz ultra-wideband CMOS circulator with differential compensation transistors and differential delay lines.
Authors: Li, Zhengyang1 (AUTHOR), Zhang, Youming1,2 (AUTHOR), Huang, Fengyi1,2 (AUTHOR) fyhuang@seu.edu.cn
Source: AEU: International Journal of Electronics & Communications. Dec2025, Vol. 202, pN.PAG-N.PAG. 1p.
Subjects: Ultra-wideband devices, Circulators (Electrical engineering), Delay lines, Broadband communication systems, Transistors, Complementary metal oxide semiconductors
Abstract: An ultra-wideband circulator with high TX-to-RX isolation based on an improved structure of sequentially switched delay lines (SSDL) is presented. Novel differential compensation transistors (DCTs) are introduced to cancel the TX signal leakage through the parasitic capacitors of the main switches. To optimize the TX-to-RX isolation over a large bandwidth, a differential delay line (DDL) based on delay compensation technique is proposed to achieve a large delay-bandwidth product (DBW) and a low delay variation (DV). The circulator circuit is implemented in a 40-nm CMOS process with excellent TX-to-RX isolation and a bandwidth substantially larger than the previously reported results, while other performances are comparable to the prior arts. The circulator circuit achieves >24 dB TX-to-RX isolation over the frequency band of 0.05–20 GHz. The TX-to-ANT and ANT-to-RX losses are 4.2–8.3 dB and 4.2–8.7 dB. The circulator exhibits a high TX-induced ANT-RX compression of 10.1–16.8 dBm across the frequency band. The measured input power 1-dB compression points (IP1dB) for TX-to-ANT and ANT-to-RX are 2.1–8.3 dBm and 2.4–7.3 dBm, respectively, with the corresponding input third-order intercept points (IIP3) of 15.6–22.1 dBm and 15.4–22.4 dBm. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:An ultra-wideband circulator with high TX-to-RX isolation based on an improved structure of sequentially switched delay lines (SSDL) is presented. Novel differential compensation transistors (DCTs) are introduced to cancel the TX signal leakage through the parasitic capacitors of the main switches. To optimize the TX-to-RX isolation over a large bandwidth, a differential delay line (DDL) based on delay compensation technique is proposed to achieve a large delay-bandwidth product (DBW) and a low delay variation (DV). The circulator circuit is implemented in a 40-nm CMOS process with excellent TX-to-RX isolation and a bandwidth substantially larger than the previously reported results, while other performances are comparable to the prior arts. The circulator circuit achieves >24 dB TX-to-RX isolation over the frequency band of 0.05–20 GHz. The TX-to-ANT and ANT-to-RX losses are 4.2–8.3 dB and 4.2–8.7 dB. The circulator exhibits a high TX-induced ANT-RX compression of 10.1–16.8 dBm across the frequency band. The measured input power 1-dB compression points (IP1dB) for TX-to-ANT and ANT-to-RX are 2.1–8.3 dBm and 2.4–7.3 dBm, respectively, with the corresponding input third-order intercept points (IIP3) of 15.6–22.1 dBm and 15.4–22.4 dBm. [ABSTRACT FROM AUTHOR]
ISSN:14348411
DOI:10.1016/j.aeue.2025.156015