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Enhanced performance of InZnSnO thin-film-transistors by designing a dual-channel-layer InSnO/InZnSnO with Xenon pulsed-light-annealing.

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Title: Enhanced performance of InZnSnO thin-film-transistors by designing a dual-channel-layer InSnO/InZnSnO with Xenon pulsed-light-annealing.
Authors: Fan, Ching-Lin1,2 (AUTHOR) clfan@mail.ntust.edu.tw, Yu, Xiang-Wei1 (AUTHOR), Tsai, Yung-Sheng1 (AUTHOR), Chen, Yan-Quan1 (AUTHOR), Chen, Hung-Yi1 (AUTHOR), Shih, Jiun-Hann2 (AUTHOR)
Source: Materials Science in Semiconductor Processing. Mar2026, Vol. 203, pN.PAG-N.PAG. 1p.
Subjects: Thin film transistors, Indium tin oxide, Scattering (Physics), Layer structure (Solids), Mathematical optimization
Abstract: Highly conductive amorphous oxide semiconductor InZnSnO (IZTO) is a promising channel material for high-mobility thin-film transistors (TFTs). To enhance the IZTO TFTs' performance, we conduct a InSnO/InZnSnO (ITO/IZTO) dual-channel layer with Xenon pulsed-light annealing (PLA) to enhance device performance in this study. The proposed optimal dual-channel layer is composed of a 5-nm-thick ITO layer and 10-nm-thick IZTO layer. The dual-channel layer ITO/IZTO effectively reduces carrier scattering and trapping at the interface between gate insulator and channel layer by the accumulation channel formed at the heterointerface between ITO and IZTO layer. Furthermore, a low-thermal budget PLA process is employed to significantly reduce the defect states of the dual-channel layer, resulting in the enhanced device performance and reliability. The optimized performance of ITO/IZTO TFT with PLA treatment exhibits a linear mobility (μ lin) of 45.48 cm2/V·s, a threshold voltage (V th) of 0.13 V, and an on/off current ratio (I on /I off) exceeding 109. In addition, the PLA-treated ITO/IZTO TFTs' reliability under positive bias stress (PBS) and negative bias stress (NBS) is significantly enhanced, with threshold voltage shifts reduced to 0.34 V and −1.33 V under PBS and NBS, respectively. The proposed scheme of the dual-channel layer ITO/IZTO with PLA treatment can reduce manufacturing costs and overall thermal budget and simultaneously enhance performance of the IZTO TFTs, which is a good candidate for the performance improvement of IZTO TFT. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:Highly conductive amorphous oxide semiconductor InZnSnO (IZTO) is a promising channel material for high-mobility thin-film transistors (TFTs). To enhance the IZTO TFTs' performance, we conduct a InSnO/InZnSnO (ITO/IZTO) dual-channel layer with Xenon pulsed-light annealing (PLA) to enhance device performance in this study. The proposed optimal dual-channel layer is composed of a 5-nm-thick ITO layer and 10-nm-thick IZTO layer. The dual-channel layer ITO/IZTO effectively reduces carrier scattering and trapping at the interface between gate insulator and channel layer by the accumulation channel formed at the heterointerface between ITO and IZTO layer. Furthermore, a low-thermal budget PLA process is employed to significantly reduce the defect states of the dual-channel layer, resulting in the enhanced device performance and reliability. The optimized performance of ITO/IZTO TFT with PLA treatment exhibits a linear mobility (μ lin) of 45.48 cm2/V·s, a threshold voltage (V th) of 0.13 V, and an on/off current ratio (I on /I off) exceeding 109. In addition, the PLA-treated ITO/IZTO TFTs' reliability under positive bias stress (PBS) and negative bias stress (NBS) is significantly enhanced, with threshold voltage shifts reduced to 0.34 V and −1.33 V under PBS and NBS, respectively. The proposed scheme of the dual-channel layer ITO/IZTO with PLA treatment can reduce manufacturing costs and overall thermal budget and simultaneously enhance performance of the IZTO TFTs, which is a good candidate for the performance improvement of IZTO TFT. [ABSTRACT FROM AUTHOR]
ISSN:13698001
DOI:10.1016/j.mssp.2025.110195