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Enhanced performance of InZnSnO thin-film-transistors by designing a dual-channel-layer InSnO/InZnSnO with Xenon pulsed-light-annealing.

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Title: Enhanced performance of InZnSnO thin-film-transistors by designing a dual-channel-layer InSnO/InZnSnO with Xenon pulsed-light-annealing.
Authors: Fan, Ching-Lin1,2 (AUTHOR) clfan@mail.ntust.edu.tw, Yu, Xiang-Wei1 (AUTHOR), Tsai, Yung-Sheng1 (AUTHOR), Chen, Yan-Quan1 (AUTHOR), Chen, Hung-Yi1 (AUTHOR), Shih, Jiun-Hann2 (AUTHOR)
Source: Materials Science in Semiconductor Processing. Mar2026, Vol. 203, pN.PAG-N.PAG. 1p.
Subjects: Thin film transistors, Indium tin oxide, Scattering (Physics), Layer structure (Solids), Mathematical optimization
Abstract: Highly conductive amorphous oxide semiconductor InZnSnO (IZTO) is a promising channel material for high-mobility thin-film transistors (TFTs). To enhance the IZTO TFTs' performance, we conduct a InSnO/InZnSnO (ITO/IZTO) dual-channel layer with Xenon pulsed-light annealing (PLA) to enhance device performance in this study. The proposed optimal dual-channel layer is composed of a 5-nm-thick ITO layer and 10-nm-thick IZTO layer. The dual-channel layer ITO/IZTO effectively reduces carrier scattering and trapping at the interface between gate insulator and channel layer by the accumulation channel formed at the heterointerface between ITO and IZTO layer. Furthermore, a low-thermal budget PLA process is employed to significantly reduce the defect states of the dual-channel layer, resulting in the enhanced device performance and reliability. The optimized performance of ITO/IZTO TFT with PLA treatment exhibits a linear mobility (μ lin) of 45.48 cm2/V·s, a threshold voltage (V th) of 0.13 V, and an on/off current ratio (I on /I off) exceeding 109. In addition, the PLA-treated ITO/IZTO TFTs' reliability under positive bias stress (PBS) and negative bias stress (NBS) is significantly enhanced, with threshold voltage shifts reduced to 0.34 V and −1.33 V under PBS and NBS, respectively. The proposed scheme of the dual-channel layer ITO/IZTO with PLA treatment can reduce manufacturing costs and overall thermal budget and simultaneously enhance performance of the IZTO TFTs, which is a good candidate for the performance improvement of IZTO TFT. [ABSTRACT FROM AUTHOR]
Copyright of Materials Science in Semiconductor Processing is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Engineering Source
An: 189648297
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PubTypeId: academicJournal
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  Data: Enhanced performance of InZnSnO thin-film-transistors by designing a dual-channel-layer InSnO/InZnSnO with Xenon pulsed-light-annealing.
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  Data: <searchLink fieldCode="AR" term="%22Fan%2C+Ching-Lin%22">Fan, Ching-Lin</searchLink><relatesTo>1,2</relatesTo> (AUTHOR)<i> clfan@mail.ntust.edu.tw</i><br /><searchLink fieldCode="AR" term="%22Yu%2C+Xiang-Wei%22">Yu, Xiang-Wei</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Tsai%2C+Yung-Sheng%22">Tsai, Yung-Sheng</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Chen%2C+Yan-Quan%22">Chen, Yan-Quan</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Chen%2C+Hung-Yi%22">Chen, Hung-Yi</searchLink><relatesTo>1</relatesTo> (AUTHOR)<br /><searchLink fieldCode="AR" term="%22Shih%2C+Jiun-Hann%22">Shih, Jiun-Hann</searchLink><relatesTo>2</relatesTo> (AUTHOR)
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  Data: <searchLink fieldCode="JN" term="%22Materials+Science+in+Semiconductor+Processing%22">Materials Science in Semiconductor Processing</searchLink>. Mar2026, Vol. 203, pN.PAG-N.PAG. 1p.
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  Data: <searchLink fieldCode="DE" term="%22Thin+film+transistors%22">Thin film transistors</searchLink><br /><searchLink fieldCode="DE" term="%22Indium+tin+oxide%22">Indium tin oxide</searchLink><br /><searchLink fieldCode="DE" term="%22Scattering+%28Physics%29%22">Scattering (Physics)</searchLink><br /><searchLink fieldCode="DE" term="%22Layer+structure+%28Solids%29%22">Layer structure (Solids)</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+optimization%22">Mathematical optimization</searchLink>
– Name: Abstract
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  Data: Highly conductive amorphous oxide semiconductor InZnSnO (IZTO) is a promising channel material for high-mobility thin-film transistors (TFTs). To enhance the IZTO TFTs' performance, we conduct a InSnO/InZnSnO (ITO/IZTO) dual-channel layer with Xenon pulsed-light annealing (PLA) to enhance device performance in this study. The proposed optimal dual-channel layer is composed of a 5-nm-thick ITO layer and 10-nm-thick IZTO layer. The dual-channel layer ITO/IZTO effectively reduces carrier scattering and trapping at the interface between gate insulator and channel layer by the accumulation channel formed at the heterointerface between ITO and IZTO layer. Furthermore, a low-thermal budget PLA process is employed to significantly reduce the defect states of the dual-channel layer, resulting in the enhanced device performance and reliability. The optimized performance of ITO/IZTO TFT with PLA treatment exhibits a linear mobility (μ lin) of 45.48 cm2/V·s, a threshold voltage (V th) of 0.13 V, and an on/off current ratio (I on /I off) exceeding 109. In addition, the PLA-treated ITO/IZTO TFTs' reliability under positive bias stress (PBS) and negative bias stress (NBS) is significantly enhanced, with threshold voltage shifts reduced to 0.34 V and −1.33 V under PBS and NBS, respectively. The proposed scheme of the dual-channel layer ITO/IZTO with PLA treatment can reduce manufacturing costs and overall thermal budget and simultaneously enhance performance of the IZTO TFTs, which is a good candidate for the performance improvement of IZTO TFT. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
  Group: Ab
  Data: <i>Copyright of Materials Science in Semiconductor Processing is the property of Pergamon Press - An Imprint of Elsevier Science and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1016/j.mssp.2025.110195
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        Text: English
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        StartPage: N.PAG
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      – SubjectFull: Thin film transistors
        Type: general
      – SubjectFull: Indium tin oxide
        Type: general
      – SubjectFull: Scattering (Physics)
        Type: general
      – SubjectFull: Layer structure (Solids)
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      – SubjectFull: Mathematical optimization
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      – TitleFull: Enhanced performance of InZnSnO thin-film-transistors by designing a dual-channel-layer InSnO/InZnSnO with Xenon pulsed-light-annealing.
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            NameFull: Fan, Ching-Lin
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            NameFull: Yu, Xiang-Wei
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            – D: 01
              M: 03
              Text: Mar2026
              Type: published
              Y: 2026
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              Value: 203
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            – TitleFull: Materials Science in Semiconductor Processing
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