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Design and optimization of in-memory half-adder and full-adder circuits using 8T and 8+T SRAM cells for enhanced logic operations.

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Title: Design and optimization of in-memory half-adder and full-adder circuits using 8T and 8+T SRAM cells for enhanced logic operations.
Authors: Desai, Kushal1 (AUTHOR) 202311059@daiict.ac.in, Agrawal, Yash1 (AUTHOR) yash_agrawal@daiict.ac.in, Rajendran, Sreeja1 (AUTHOR) sreeja_rajendran@daiict.ac.in, Palaparthy, Vinay1 (AUTHOR) vinay_shrinivas@daiict.ac.in
Source: Microsystem Technologies. Dec2025, Vol. 31 Issue 12, p3835-3846. 12p.
Subjects: Adders (Digital electronics), Static random access memory, Computer architecture, Binary operations, Mechanical efficiency
Abstract: This paper presents an optimized in-memory computing (IMC) architecture for Half Adder and Full Adder implementation based on 8T and 8+T SRAM cells respectively. By leveraging bitline differentials and precise Read Word Line (RWL) control, fundamental Boolean operations such as AND, OR, XOR, NOR, and NAND are efficiently executed directly within the memory array, reducing complexity, latency, and power consumption. A conditional XOR approach is used for SUM generation, while optimized carry logic minimizes the critical path delay. A 4-bit ripple carry adder (RCA) is constructed using these memory-integrated Full Adder units, achieving a 33% reduction in transistor count compared to conventional designs. Experimental evaluation using 180 nm UMC technology demonstrates significant improvements in delay and energy efficiency, with up to 83.12% faster carry generation and 43.51% faster sum computation for half-adders. The proposed design offers a 23% reduction in power-delay product (PDP) for 4-bit RCAs, making it highly suitable for high-performance, low-power in-memory computing systems. Timing optimization strategies are also discussed to address minor carry signal anomalies, ensuring robust operation across all adder stages. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:This paper presents an optimized in-memory computing (IMC) architecture for Half Adder and Full Adder implementation based on 8T and 8+T SRAM cells respectively. By leveraging bitline differentials and precise Read Word Line (RWL) control, fundamental Boolean operations such as AND, OR, XOR, NOR, and NAND are efficiently executed directly within the memory array, reducing complexity, latency, and power consumption. A conditional XOR approach is used for SUM generation, while optimized carry logic minimizes the critical path delay. A 4-bit ripple carry adder (RCA) is constructed using these memory-integrated Full Adder units, achieving a 33% reduction in transistor count compared to conventional designs. Experimental evaluation using 180 nm UMC technology demonstrates significant improvements in delay and energy efficiency, with up to 83.12% faster carry generation and 43.51% faster sum computation for half-adders. The proposed design offers a 23% reduction in power-delay product (PDP) for 4-bit RCAs, making it highly suitable for high-performance, low-power in-memory computing systems. Timing optimization strategies are also discussed to address minor carry signal anomalies, ensuring robust operation across all adder stages. [ABSTRACT FROM AUTHOR]
ISSN:09467076
DOI:10.1007/s00542-025-05957-3