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Design and optimization of in-memory half-adder and full-adder circuits using 8T and 8+T SRAM cells for enhanced logic operations.

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Title: Design and optimization of in-memory half-adder and full-adder circuits using 8T and 8+T SRAM cells for enhanced logic operations.
Authors: Desai, Kushal1 (AUTHOR) 202311059@daiict.ac.in, Agrawal, Yash1 (AUTHOR) yash_agrawal@daiict.ac.in, Rajendran, Sreeja1 (AUTHOR) sreeja_rajendran@daiict.ac.in, Palaparthy, Vinay1 (AUTHOR) vinay_shrinivas@daiict.ac.in
Source: Microsystem Technologies. Dec2025, Vol. 31 Issue 12, p3835-3846. 12p.
Subjects: Adders (Digital electronics), Static random access memory, Computer architecture, Binary operations, Mechanical efficiency
Abstract: This paper presents an optimized in-memory computing (IMC) architecture for Half Adder and Full Adder implementation based on 8T and 8+T SRAM cells respectively. By leveraging bitline differentials and precise Read Word Line (RWL) control, fundamental Boolean operations such as AND, OR, XOR, NOR, and NAND are efficiently executed directly within the memory array, reducing complexity, latency, and power consumption. A conditional XOR approach is used for SUM generation, while optimized carry logic minimizes the critical path delay. A 4-bit ripple carry adder (RCA) is constructed using these memory-integrated Full Adder units, achieving a 33% reduction in transistor count compared to conventional designs. Experimental evaluation using 180 nm UMC technology demonstrates significant improvements in delay and energy efficiency, with up to 83.12% faster carry generation and 43.51% faster sum computation for half-adders. The proposed design offers a 23% reduction in power-delay product (PDP) for 4-bit RCAs, making it highly suitable for high-performance, low-power in-memory computing systems. Timing optimization strategies are also discussed to address minor carry signal anomalies, ensuring robust operation across all adder stages. [ABSTRACT FROM AUTHOR]
Copyright of Microsystem Technologies is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Database: Engineering Source
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DbLabel: Engineering Source
An: 190299073
AccessLevel: 6
PubType: Academic Journal
PubTypeId: academicJournal
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  Data: Design and optimization of in-memory half-adder and full-adder circuits using 8T and 8+T SRAM cells for enhanced logic operations.
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  Data: <searchLink fieldCode="AR" term="%22Desai%2C+Kushal%22">Desai, Kushal</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> 202311059@daiict.ac.in</i><br /><searchLink fieldCode="AR" term="%22Agrawal%2C+Yash%22">Agrawal, Yash</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> yash_agrawal@daiict.ac.in</i><br /><searchLink fieldCode="AR" term="%22Rajendran%2C+Sreeja%22">Rajendran, Sreeja</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> sreeja_rajendran@daiict.ac.in</i><br /><searchLink fieldCode="AR" term="%22Palaparthy%2C+Vinay%22">Palaparthy, Vinay</searchLink><relatesTo>1</relatesTo> (AUTHOR)<i> vinay_shrinivas@daiict.ac.in</i>
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  Data: <searchLink fieldCode="JN" term="%22Microsystem+Technologies%22">Microsystem Technologies</searchLink>. Dec2025, Vol. 31 Issue 12, p3835-3846. 12p.
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  Data: <searchLink fieldCode="DE" term="%22Adders+%28Digital+electronics%29%22">Adders (Digital electronics)</searchLink><br /><searchLink fieldCode="DE" term="%22Static+random+access+memory%22">Static random access memory</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Binary+operations%22">Binary operations</searchLink><br /><searchLink fieldCode="DE" term="%22Mechanical+efficiency%22">Mechanical efficiency</searchLink>
– Name: Abstract
  Label: Abstract
  Group: Ab
  Data: This paper presents an optimized in-memory computing (IMC) architecture for Half Adder and Full Adder implementation based on 8T and 8+T SRAM cells respectively. By leveraging bitline differentials and precise Read Word Line (RWL) control, fundamental Boolean operations such as AND, OR, XOR, NOR, and NAND are efficiently executed directly within the memory array, reducing complexity, latency, and power consumption. A conditional XOR approach is used for SUM generation, while optimized carry logic minimizes the critical path delay. A 4-bit ripple carry adder (RCA) is constructed using these memory-integrated Full Adder units, achieving a 33% reduction in transistor count compared to conventional designs. Experimental evaluation using 180 nm UMC technology demonstrates significant improvements in delay and energy efficiency, with up to 83.12% faster carry generation and 43.51% faster sum computation for half-adders. The proposed design offers a 23% reduction in power-delay product (PDP) for 4-bit RCAs, making it highly suitable for high-performance, low-power in-memory computing systems. Timing optimization strategies are also discussed to address minor carry signal anomalies, ensuring robust operation across all adder stages. [ABSTRACT FROM AUTHOR]
– Name: AbstractSuppliedCopyright
  Label:
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  Data: <i>Copyright of Microsystem Technologies is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Type: general
      – SubjectFull: Static random access memory
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      – SubjectFull: Computer architecture
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      – SubjectFull: Binary operations
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              M: 12
              Text: Dec2025
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