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Dynamic Header Switch to Influence Switching Current Profile of an IC Chip.

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Title: Dynamic Header Switch to Influence Switching Current Profile of an IC Chip.
Authors: Yadav, Vijay Pratap1 (AUTHOR) vijayvy07@gmail.com, Singh, Vipin Kumar1 (AUTHOR) singhvipinism@gmail.com, Kumar, Ashish Ranjan1 (AUTHOR) ashish.ranjan01@hotmail.com, Pokhrel, Tika Ram2 (AUTHOR) tikaram9923@gmail.com, Metya, Sanjeev Kumar1 (AUTHOR) smetya@gmail.com, Majumder, Alak1 (AUTHOR) majumder.alak@gmail.com
Source: Circuits, Systems & Signal Processing. Jan2026, Vol. 45 Issue 1, p393-417. 25p.
Subjects: High performance processors, Power resources management, Model validation, Voltage control, Electric transients
Abstract: Inrush currents, which occurs during transitions from sleep to active states, always introduce power noise and voltage instability, jeopardizing the stability of core and escalating error susceptibility in high-performance processors. This phenomenon aggravates power delivery challenges and lowers system reliability. The study in this article unveils an innovative Power Gating (PG) technique utilizing a delay based soft-start header to alleviate the effects of inrush current. By enabling a steady and controlled current ramp-up, the proposed scheme ensures seamless activation while optimizing associated disruptions. This technique strategically manages the width (W) of header sleep transistor into smaller divisions—such as W/2, W/5, W/10, or W/20—activating each segment sequentially. We have incorporated fixed-delay cells between these segments, introducing intentional delays to stagger activation. This approach effectively distributes current demands over time, arresting the simultaneous activation of the entire transistor width and massively curbing down peak inrush currents. Simulations carried out using the UMC65nm CMOS on Cadence Virtuoso validate the approach. Whie using a 20% sleep signal, the proposed scheme achieves substantial reductions in peak inrush currents—54.55%, 82.01%, 89.94%, and 93.65% across Plans 1–4, respectively—compared to conventional power gating. The plans are validated through testing on ISCAS benchmarks and multiple switching of cores having 64 bit adder. [ABSTRACT FROM AUTHOR]
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Database: Engineering Source
Description
Abstract:Inrush currents, which occurs during transitions from sleep to active states, always introduce power noise and voltage instability, jeopardizing the stability of core and escalating error susceptibility in high-performance processors. This phenomenon aggravates power delivery challenges and lowers system reliability. The study in this article unveils an innovative Power Gating (PG) technique utilizing a delay based soft-start header to alleviate the effects of inrush current. By enabling a steady and controlled current ramp-up, the proposed scheme ensures seamless activation while optimizing associated disruptions. This technique strategically manages the width (W) of header sleep transistor into smaller divisions—such as W/2, W/5, W/10, or W/20—activating each segment sequentially. We have incorporated fixed-delay cells between these segments, introducing intentional delays to stagger activation. This approach effectively distributes current demands over time, arresting the simultaneous activation of the entire transistor width and massively curbing down peak inrush currents. Simulations carried out using the UMC65nm CMOS on Cadence Virtuoso validate the approach. Whie using a 20% sleep signal, the proposed scheme achieves substantial reductions in peak inrush currents—54.55%, 82.01%, 89.94%, and 93.65% across Plans 1–4, respectively—compared to conventional power gating. The plans are validated through testing on ISCAS benchmarks and multiple switching of cores having 64 bit adder. [ABSTRACT FROM AUTHOR]
ISSN:0278081X
DOI:10.1007/s00034-025-03242-2