FPGA Based True Random Number Generator Using Programmable Ring Oscillator Delays.

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Title:	FPGA Based True Random Number Generator Using Programmable Ring Oscillator Delays.
Authors:	Reddy, V. Sagar¹ vsagarreddy1990@gmail.com, Vamsi, H. K. Raghu² hkraghuvamsik@adityauniversity.in, Ganesh, Ch¹ ganesh_ch@vnrvjiet.in, Divya, Dontika¹ ddivyadontika@gmail.com, Vasanth, Munukuntla³ munukuntlavasanth1@gmail.com, Senapati, Ranjan K.¹ ranjan_ks@vnrvjiet.in
Source:	Engineering Letters. May2026, Vol. 34 Issue 5, p2064-2071. 8p.
Subjects:	Random number generators, Field programmable gate arrays, Hardware, Electronic data processing
Abstract:	True random number generators (TRNGs) are critical components in cryptographic systems, secure communications, and hardware security. This paper presents an FPGA-based TRNG implemented on a Xilinx Artix-7 device, utilizing the flexibility of 6-input look-up tables (LUTs) to construct programmable delay lines (PDLs) within oscillator rings. The proposed architecture increases the number of delay configurations and oscillator rings compared to conventional 4-input LUT designs, enhancing entropy and throughput. A dual-path post-processing framework is introduced, enabling direct comparison between the Von Neumann corrector and a cryptographically secure Keccak (SHA-3)-based extractor. A multiplexer-based scheme allows real-time selection of the post-processing output for evaluation. Experimental results show that the Keccak-based extractor achieves higher throughput while maintaining statistical quality, passing the NIST SP 800-22 test suite. The design improves entropy rate and output bandwidth while preserving resource efficiency, offering a flexible and robust solution for high-quality random number generation in cryptographic hardware. [ABSTRACT FROM AUTHOR]
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Database:	Engineering Source

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Abstract:	True random number generators (TRNGs) are critical components in cryptographic systems, secure communications, and hardware security. This paper presents an FPGA-based TRNG implemented on a Xilinx Artix-7 device, utilizing the flexibility of 6-input look-up tables (LUTs) to construct programmable delay lines (PDLs) within oscillator rings. The proposed architecture increases the number of delay configurations and oscillator rings compared to conventional 4-input LUT designs, enhancing entropy and throughput. A dual-path post-processing framework is introduced, enabling direct comparison between the Von Neumann corrector and a cryptographically secure Keccak (SHA-3)-based extractor. A multiplexer-based scheme allows real-time selection of the post-processing output for evaluation. Experimental results show that the Keccak-based extractor achieves higher throughput while maintaining statistical quality, passing the NIST SP 800-22 test suite. The design improves entropy rate and output bandwidth while preserving resource efficiency, offering a flexible and robust solution for high-quality random number generation in cryptographic hardware. [ABSTRACT FROM AUTHOR]
ISSN:	1816093X