FPGA Based True Random Number Generator Using Programmable Ring Oscillator Delays.
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| Title: | FPGA Based True Random Number Generator Using Programmable Ring Oscillator Delays. |
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| Authors: | Reddy, V. Sagar1 vsagarreddy1990@gmail.com, Vamsi, H. K. Raghu2 hkraghuvamsik@adityauniversity.in, Ganesh, Ch1 ganesh_ch@vnrvjiet.in, Divya, Dontika1 ddivyadontika@gmail.com, Vasanth, Munukuntla3 munukuntlavasanth1@gmail.com, Senapati, Ranjan K.1 ranjan_ks@vnrvjiet.in |
| Source: | Engineering Letters. May2026, Vol. 34 Issue 5, p2064-2071. 8p. |
| Subjects: | Random number generators, Field programmable gate arrays, Hardware, Electronic data processing |
| Abstract: | True random number generators (TRNGs) are critical components in cryptographic systems, secure communications, and hardware security. This paper presents an FPGA-based TRNG implemented on a Xilinx Artix-7 device, utilizing the flexibility of 6-input look-up tables (LUTs) to construct programmable delay lines (PDLs) within oscillator rings. The proposed architecture increases the number of delay configurations and oscillator rings compared to conventional 4-input LUT designs, enhancing entropy and throughput. A dual-path post-processing framework is introduced, enabling direct comparison between the Von Neumann corrector and a cryptographically secure Keccak (SHA-3)-based extractor. A multiplexer-based scheme allows real-time selection of the post-processing output for evaluation. Experimental results show that the Keccak-based extractor achieves higher throughput while maintaining statistical quality, passing the NIST SP 800-22 test suite. The design improves entropy rate and output bandwidth while preserving resource efficiency, offering a flexible and robust solution for high-quality random number generation in cryptographic hardware. [ABSTRACT FROM AUTHOR] |
| Copyright of Engineering Letters is the property of International Association of Engineers (IAENG) and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Engineering Source |
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| Header | DbId: egs DbLabel: Engineering Source An: 193453960 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 0 |
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| Items | – Name: Title Label: Title Group: Ti Data: FPGA Based True Random Number Generator Using Programmable Ring Oscillator Delays. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Reddy%2C+V%2E+Sagar%22">Reddy, V. Sagar</searchLink><relatesTo>1</relatesTo><i> vsagarreddy1990@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Vamsi%2C+H%2E+K%2E+Raghu%22">Vamsi, H. K. Raghu</searchLink><relatesTo>2</relatesTo><i> hkraghuvamsik@adityauniversity.in</i><br /><searchLink fieldCode="AR" term="%22Ganesh%2C+Ch%22">Ganesh, Ch</searchLink><relatesTo>1</relatesTo><i> ganesh_ch@vnrvjiet.in</i><br /><searchLink fieldCode="AR" term="%22Divya%2C+Dontika%22">Divya, Dontika</searchLink><relatesTo>1</relatesTo><i> ddivyadontika@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Vasanth%2C+Munukuntla%22">Vasanth, Munukuntla</searchLink><relatesTo>3</relatesTo><i> munukuntlavasanth1@gmail.com</i><br /><searchLink fieldCode="AR" term="%22Senapati%2C+Ranjan+K%2E%22">Senapati, Ranjan K.</searchLink><relatesTo>1</relatesTo><i> ranjan_ks@vnrvjiet.in</i> – Name: TitleSource Label: Source Group: Src Data: <searchLink fieldCode="JN" term="%22Engineering+Letters%22">Engineering Letters</searchLink>. May2026, Vol. 34 Issue 5, p2064-2071. 8p. – Name: Subject Label: Subjects Group: Su Data: <searchLink fieldCode="DE" term="%22Random+number+generators%22">Random number generators</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Hardware%22">Hardware</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+data+processing%22">Electronic data processing</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: True random number generators (TRNGs) are critical components in cryptographic systems, secure communications, and hardware security. This paper presents an FPGA-based TRNG implemented on a Xilinx Artix-7 device, utilizing the flexibility of 6-input look-up tables (LUTs) to construct programmable delay lines (PDLs) within oscillator rings. The proposed architecture increases the number of delay configurations and oscillator rings compared to conventional 4-input LUT designs, enhancing entropy and throughput. A dual-path post-processing framework is introduced, enabling direct comparison between the Von Neumann corrector and a cryptographically secure Keccak (SHA-3)-based extractor. A multiplexer-based scheme allows real-time selection of the post-processing output for evaluation. Experimental results show that the Keccak-based extractor achieves higher throughput while maintaining statistical quality, passing the NIST SP 800-22 test suite. The design improves entropy rate and output bandwidth while preserving resource efficiency, offering a flexible and robust solution for high-quality random number generation in cryptographic hardware. [ABSTRACT FROM AUTHOR] – Name: AbstractSuppliedCopyright Label: Group: Ab Data: <i>Copyright of Engineering Letters is the property of International Association of Engineers (IAENG) and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 8 StartPage: 2064 Subjects: – SubjectFull: Random number generators Type: general – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Hardware Type: general – SubjectFull: Electronic data processing Type: general Titles: – TitleFull: FPGA Based True Random Number Generator Using Programmable Ring Oscillator Delays. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Reddy, V. Sagar – PersonEntity: Name: NameFull: Vamsi, H. K. Raghu – PersonEntity: Name: NameFull: Ganesh, Ch – PersonEntity: Name: NameFull: Divya, Dontika – PersonEntity: Name: NameFull: Vasanth, Munukuntla – PersonEntity: Name: NameFull: Senapati, Ranjan K. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 05 Text: May2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 1816093X Numbering: – Type: volume Value: 34 – Type: issue Value: 5 Titles: – TitleFull: Engineering Letters Type: main |
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